IEEE Solid-States Circuits Magazine - Summer 2021 - 66

circuits and systems to redefine how
computation can be done. Looking
forward, the realm of " cognitive computing "
is inspired by new and continually
emerging understanding of
advanced brain and neuronal behavior
that enables efficient and real-time
learning and reaction. This call for
papers is on emerging hardware for
cognitive computing. The focus and
emphasis of these special-topic papers
is beyond-deep-neural-network processing
as well as beyond-multiweight
synapses and basic neuron integrating,
firing, and stochasticity. The submission
deadline for this special issue
was 15 July.
ACM Transactions on Design
Automation of Electronic Systems-
Special Issue on High-Level Synthesis
for FPGA: Next-Generation
Technologies and Applications
Due to the end of Dennard scaling
and Moore's law, complex hyperpipelined
processors are increasingly
replaced by heterogeneous
system-on-chip (SoC) architectures
with many specialized components.
Field-programmable gate
array (FPGA) devices are becoming
common targets for these systems
since they allow fast turnaround
times, field upgradability, and easy
deployment of hardware/software
solutions. To cope with the increasing
complexity of such systems,
designers need to raise the abstraction
level from custom design
flows to high-level approaches.
High-level synthesis (HLS) is a popular
method that allows designers
to describe the functionality of a
component at
the software level
and automatically generate the corresponding
hardware description,
reducing the gap between application
and hardware designers.
Since HLS has been making a great
amount of progress and an increasing
number of different application
domains are pushing designers
toward hardware acceleration, HLS
is becoming a key enabling technology
for FPGA design. Submissions
for this special issue were due by
30 June.
IEEE CEDA System Validation
and Debug Technology Committee
Presents New Standard
The IEEE System Validation and
Debug Technology Committee (SVDTC)
Debug Subcommittee has prepared
a presentation to IEEE to approve
scan and array debug standardization
efforts. The committee presented
to the IEEE Test Technology Standards
Committee (TTSC) a proposal
to approve a new IEEE standards
effort for scan and array debugging
for SoCs, " Standard for System-Level
State Extraction for Functional Validation
and Debug. " Sankaran Menon,
chair of the SVDTC Debug Subcommittee,
presented the project authorization
request for P2929, " Standard
for System-Level State Extraction for
Functional Validation and Debug " to
the TTSC, and the standardization
effort was approved. Menon started
IEEE P2929 standardization working
group meetings with about 28
attendees from academia and industry
in mid-December 2020. If you are
interested in participating, contact
him at smenon@ieee.org or sankaran
.menon@gmail.com.
66 SUMMER 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
http://ieee-ceda.org http://bit.ly/ESLSubmissions http://bit.ly/DTSubmissions
IEEE Solid-States Circuits Magazine - Summer 2021

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