IEEE Solid-States Circuits Magazine - Summer 2021 - 7
VDD
VDD
M1
A1
X
Q1
AE
(a)
X
P PP
M1
M2
M1
A1
X
M2
A1
-- Y++ -+
Y
R1
Q2
nAE
R2
Q1
AE
(b)
Q2
nAE
R1
R3
R2
Q1
AE
(c)
FIGURE 2: (a) A basic bandgap core. (b) The addition of resistors to create constant currents. (c) The addition of an output branch.
the base-emitter voltage, VT/ ,22 is
we expect ||V 1BE
BE
around .,V/15mCc
to
be relatively large at low temperatures.
With a worst-case VDD
relatively large bipolar transistors
and low collector currents to ensure a
moderate || ()./lnVV II
BE TC S
=
+ 100C,
c ||V 1BE
Second, as T goes from 0Cc to
in Figure 2(c) drops by
roughly 150 mV, whereas Vout
and M3
remains
relatively constant. The resulting difference
between the drain-source
voltages of M ,12
substantial error in ID3
large variation in V .out We will resolve
this issue through the use of a regulated
cascode structure.
Third, the offset of
A ,1
V ,1OS
in Figure
2(c) introduces an error in V .out
We have [13]
V
out1 T
=+
-+
R
R
cm
;
L VBE
1
||
R
R
1
3
31
3
VOS1E.
The contribution of V 1OS
R
R Vn
ln
(7)
can be minimized
by maximizing lnn-a remedy
that costs chip area.
Fourth, the 40-dB supply-rejection
requirement imposes a lower bound
on the operation amplifier (op amp)
gain in Figure 2(c). As explained next,
A1
must reach several hundred.
Fifth, the bandgap core of Figure
2(b) and (c) can indefinitely
remain off after powerup if VX
VY begin from zero and A1
and
loses
the ability to control V .P The core
FIGURE 4: (a) A test setup for studying PSRR and (b) the PSRR of the basic core.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2021
7
(a)
+
VDD
-
A1
- +
XY
1
gm1
R1
1
gm2
M1
P
M2
W
L
50 µm
=
120 nm
A1 = 100
(a)
leads to a
and, hence, a
P
M1
A1
35 µA
X
R1
Q1
4×
Q2
64×
-+
35 µA
Y
2 kΩ
M2
of 0.95 V,
this leaves little voltage headroom for
M1
and M .2 We must therefore select
must therefore incorporate a startup
circuit.
Core Design
The design of the core presented in Figure
2(a) begins with the choice of the
VDD
0.5
0.55
0.6
0.65
0.7
0.75
0.8
Temperature (°C)
(b)
FIGURE 3: (a) The preliminary core design and (b) its internal voltages versus T.
-19.5
-20.5
-20
-21.5
-21
-22.5
-22
-23
105
106
107
Frequency (Hz)
(b)
108
109
bipolar transistors' dimensions and
emitter area ratio, n. From the issues
outlined in the previous section, we
note that the limited voltage headroom
makes it desirable to minimize
||VBE
and, hence, maximize the emitter
Q2
nAE
Y
R1
R3
RL
M2
VDD
M3
Vout
VX
VP
020406080 100
PSRR (dB)
Voltage (V)
IEEE Solid-States Circuits Magazine - Summer 2021
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2021
Contents
IEEE Solid-States Circuits Magazine - Summer 2021 - Cover1
IEEE Solid-States Circuits Magazine - Summer 2021 - Cover2
IEEE Solid-States Circuits Magazine - Summer 2021 - Contents
IEEE Solid-States Circuits Magazine - Summer 2021 - 2
IEEE Solid-States Circuits Magazine - Summer 2021 - 3
IEEE Solid-States Circuits Magazine - Summer 2021 - 4
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