IEEE Solid-States Circuits Magazine - Summer 2021 - 8

areas. But the op amp-offset issue
demands that n also be large, leading
to an area-hungry solution. As a reasonable
compromise, we select four
unit transistors for Q1
, each having
VDD
P
M1
Ma
A
X
MX MY
Q1
4×
50 µA
=
W
L
50 µm
ISS
120 nm
FIGURE 5: The bandgap core with a
simple OTA.
0.5
0.55
0.6
0.65
0.7
0.75
0.8
020406080
Temperature (°C)
FIGURE 6: The internal voltages of the bandgap core versus T.
10
20
-60
-50
-40
-30
-20
-10
105
106
107
Frequency (Hz)
FIGURE 7: The PSRR responses of the core for different temperatures.
8
SUMMER 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
FIGURE 8: The bootstrapping of node P by
the OTA active load.
108
1
Q2
64×
This result carries over to (7). Nevertheless,
an m value substantially grea -
ter than unity also raises ||,V 1BE
exacerbating
the metal-oxide-semiconductor
(MOS) transistor voltage headroom
iss- ue at low temperatures. For examY
R
2 kΩ
Mb
M2
an emitter area of 5m 5m, andnn#
BE .
T
ln
64 units for Q .2 Thus, ||V 750mV VV mI IV m
and ln .Vn 72mV at room tempera- VI ITD S11 also increases by
ture. The weak dependence ofVnT
ple, if m 16,= ||
ln
BE1
V ln16 66mV
T
upon n suggests that the effect of
offset in (7) cannot be reduced easily
through this variable.
Another approach to lowering the
effect of the op amp offset in Figure
2(a) involves scaling ID1
up with
respect to .ID2 Denoting this ratio by
m, we recognize from (2) that
||
IR ln().Vn mDT
21 =
$
(8)
=
|| ()/TD ST
11
at T 0C.=
c
fore maintain m 1=
== +
ln ()/
VOS by proper op amp design.
The next task is to select the bias
current in each branch, the value of
R ,1
and the dimensions of M1
and
M .2 Anticipating about half a dozen
bias currents in the main branches
and the op amp(s) in the final design
and bearing in mind the 1-mW power
budget, we choose || ||
II 35 ADD
12
and hence R 2k .
= . n
1 = X For the PMOS
transistors, the channel area must
be large enough to minimize mismatch
and flicker noise, and the
length must be long enough to
en sure that channel-length modulation
does not limit the supply rejection.
Based on these considerations,
we select (/ )
WL 50 120mnm.
12, = n /
Figure 3(a) depicts the prelimiVX
VA
VP
nary
core design. We simulate the
circuit while assuming an ideal
op amp having a gain of 100. Our
objective is twofold: to measure the
extreme values of
V ,X V ,Y and VP
IRD21 is doubled, but
ln
We thereand
target a low
and
to quantify the power-supply-rejection
ratio (PSRR). In Figure 3(b), VX
and VP
the temperature. (The high op amp
gain guarantees that
.
100
results reveal several points. First,
|| ||VV VVPX 11GS
-= - DS
and M2
()/WL ,12
mum value of about 230 mV, placing
M1
is adequately large. Second,
the op amp input stage must operate
properly across the common-mode
(CM) range of VX
and VY-from
around 780 mV to 620 mV. Third, the
op amp output must accommodate
the variation of VP
640 mV.
from 550 mV to
∆VDD
0 °C
50 °C
100 °C
109
VDD
P
Ma
A
∆VDD
∆VDD
Mb M1
M2
VV .)YX These
has a maxiin
saturation. That is,
are plotted as a function of
PSRR (dB)
Voltage (V)
IEEE Solid-States Circuits Magazine - Summer 2021

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