IEEE Solid-States Circuits Magazine - Summer 2021 - 9

Next, we investigate the core's supVDD
ply
rejection by constructing the setup
displayed in Figure 4. The supply
voltage varies by a small amount,
TV ,DD
and Q1
and Q2
gg
mm
12
=
with their small-signal resistances.
Note that //
and Q2 carry equal currents. If ID1
ID2 change by TI ,D we have
TT TT-= +cm
YX
D
1
=TIR ,D 1
and, hence, VA .IRTT=
to be small and V 1,2GS
DD
ID
11 because Q1
and
VV IR 11
gm21
gm
(9)
(10)
PD11 In a
well-designed circuit, we expect
T ID
TT.
P
TID . T
It follows that
.
AR
V
11
DD
is far short of
to be relatively
constant, which predicts that
VV .
(11)
We now ask, which quantity is
the " output " of interest here? Since
the drain current of M1
and M2
generate the reference voltage, we
define the PSRR as
IR
PSRR V
T
= T
.
age ofVn 72mV mV and RL
Moreover, if R1
T ln .
1
L 014
=
PSRR 014 1
=
It follows that
..A
AR
L
R
DL
DD
11
.
(12)
(13)
sustains a voltan
output
voltage of 500 mV, we have
RR/ ..
(14)
For 40 dB of rejection, A1
must
exceed 700. In practice, the PSRR is
plotted as the inverse of the previous
quantities, i.e., as the magnitude
of the transfer function from VDD
to
the output of interest.
For initial PSRR simulations, we
simply multiply the voltage variation
across R1
by .,/10 14 arriving
at the plot presented in Figure 4(b).
For supply-perturbation frequencies
up to tens of megahertz, the
PSRR is around -23 dB, which agrees
with (14). At higher frequencies,
CC
GS12GS
+
VDD changes to C 1GD
ing VX and VY
causto
bounce. The PSRR
10
20
-60
-50
-40
-30
-20
-10
in Figure 4(a) couples the
and C ,2GD
105
106
107
Frequency (Hz)
FIGURE 11: The PSRR of the core with a two-stage op amp.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2021
9
108
is
eventually copied and applied to
a resistor [e.g., RL
in Figure 2(c)] to
the desired value,
necessitating further design efforts.
Op Amp Design
Since the op amp in Figure 3(a) must
operate with input CM levels as high
as 780 mV, we select an NMOS input
stage for it. The simplest implementation
is a five-transistor operational
transconductance amplifier (OTA),
as presented in Figure 5. We assume
//
120
transistors. With a tail current of
50 μA, the op amp provides a gain of
about 20, and MX
and MY
T 100C=
c
I .SS However, at
and ||V 1,2TH
exhibit a
minimum source voltage of 350 mV
at
T 0C=
c both ||VBE
possibly pushing MX
, which is sufficient for
,
take on large values,
into the triode
region and lowering the op amp
gain. Figure 6 plots
versus T, demonstrating that VV
keeps MX
-
V ,X V ,A and VP
XA
in saturation. Figure 7
Mc
Ma
∆VDD
∆VDD
FIGURE 10: Paths from VDD
nodes of the two-stage op amp.
WL 50= nmnm for all of the
T 0C=
c 50 Cc
, and 010 Cc
to the internal
presents how the PSRR responses at
,
∆VDD
VDD
Mb
Md
FIGURE 9: A two-stage op amp for use in the bandgap reference.
Mc
are replaced
X
Ma
Ra
MX
50 µA
Rb
MY
ISS
Y
Ra = Rb = 40 kΩ
=
W
L
120 nm
50 µm
Mb
Md
To
Node P
illustrate
a degradation at low temperatures.
An interesting observation in Figure
7 is that the low-frequency PSRR
is around -35 dB at
T 0C=
c
(14) would yield (.
.
10 A14
/
, whereas
1 9dB
) / -
for A 201 = Why is the performance
better than expected? In the analysis
leading to (14), we assumed that the
op amp must multiply VV
to adjust VP
YX by A1
-
and allow it to track V .DD
However, in the circuit of Figure 5,
the OTA provides an additional
0 °C
50 °C
100 °C
109
PSRR (dB)
IEEE Solid-States Circuits Magazine - Summer 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2021
