IEEE Solid-States Circuits Magazine - Summer 2022 - 104

T
IEEE SSCS Shanghai Chapter Holds Young Scholars Forum
The IEEE Solid-State Circuits Society
(SSCS) Shanghai Chapter held a Young
Scholars Forum on 23 March 2022.
Dr. Qijing Huang, research scientist
with NVIDIA Research, presented a
talk, " Codesign of Algorithms, Hardware,
and Scheduling for Deep Learning
Applications. "
Huang's research interests include
hardware accelerators, high-level
synthesis (HLS)-based design flow,
ML/optimization-assisted compilers,
and CAD flow. Previously, she
earned her Ph.D. degree in computer
science at the University of California
(UC), Berkeley, under the supervision
of Prof. John Wawrzynek. Her
thesis work focused on novel design
and scheduling techniques for accelerating
ML algorithms on heterogeneous
spatial architecture. Before
UC Berkeley, she received her B.A.Sc.
degree in electrical and computer
engineer ing from
the University of Toronto,
where she was granted
the University of Toronto
Excellence Awards.
Dr. Qijing talked about " Co-design of Algorithms, Hardware, and Scheduling for Deep
Learning Applications " at the student forum.
Careful scheduling
and mapping
of complex
DNN models on
Abstract
In the past few years,
re searchers have increased
the complexity
of deep neural network
(DNN) models to
achieve higher accuracy.
Meanwhile, spatial architectures
continue to grow in capacity to meet
the computational requirements of
DNN workloads. Careful scheduling
and mapping of complex DNN modDigital
Object Identifier 10.1109/MSSC.2022.3179890
Date of current version: 24 August 2022
parallel hardware
architectures have
become a crucial
step in achieving
high performance
and energy
efficiency.
els on parallel hardware architectures
have become a crucial step in
achieving high performance and energy
efficiency. However, there are
significant challenges
in jointly designing
algorithms, scheduling,
and hardware
designs to achieve optimal
solutions for
accelerating deep learning
tasks. On the algorithm
side, we see the
need to design more hardware-fr
iendly models.
On the hardware side, we
see a need to shorten the
hardware design cycle to
keep up with changing algorithms. In
between, we see a need for optimal
scheduling and scheduling-informed
hardware design.
In this talk, I will discuss how we
co-optimize the full DNN acceleration
stack through a three-pronged
approach: 1) algorithm-hardware
co-design, 2) an HLS-based hardware
design methodology, and 3) hardware-constraint-driven
scheduling
and scheduling-informed hardware
design. In the first line of the work,
we co-designed efficient low-precision
DNN models and FPGA accelerators
to achieve real-time inference
performance on embedded platforms
with on-par accuracy for image classification
and object detection. In
the second line of our research, we
implemented an HLS-based accelerator
SoC design flow to quickly evaluate
different hardware design decisions.
Finally, we formulated the DNN
scheduling problem on spatial accelerators
as a mixed-integer linear program
to deterministically solve for
valid high-performance schedules.
Our results show that our approach
can significantly improve the endto-end
system performance and the
designers' productivity.
-Yun Chen
104 SUMMER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
IEEE Solid-States Circuits Magazine - Summer 2022

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