IEEE Solid-States Circuits Magazine - Summer 2022 - 14

dc voltage is a ()V 0GS
2 lower than the
input dc voltage, in the PMOS case, the
output dc voltage is a ()V 0SG
2
higher
than the input dc voltage. However, in
both cases, the open-circuit voltage
gain for ac signals is expected to be
1 V/V, which is the same as that of an
ideal voltage follower.
If we do not ignore the body
effect and the channel-length modulation,
the small-signal voltage gain
of the source follower will be somewhat
lower than 1 V/V. In fact, using
the techniques presented in the first
VDD
vin
gm, ro
vout
IB
vin
CL
gm, ro
CL
IB
vout
V
V
in
out
=
gme
gm
+
1
o
(1)
r
Since gm is always smaller than g ,me
this voltage gain is always less than
1 V/V.
Figure 3 shows simulated voltage
waveforms for an NMOS and
a PMOS source follower designed
in a generic 45-nm CMOS technology,
with the specific parameters
VDD
article in this series [1], one can easily
show that
shown in Table 1. In the case of the
NMOS,
the dc voltage of
the output
waveform is around 520 mV
lower than that of the input waveform.
This voltage difference is, in
fact, the VGS
used to bias the transistor.
The peak-to-peak value of
the output is a fraction (. )07+
of
the peak-to-peak value of the input
waveform. This reduction in voltage
gain (from an ideal of one) is
the direct consequence of the body
effect and the finite output resistance
of the transistor, as listed in
Table 1. In fact, by plugging the values
from Table 1 into (1), we get the
same voltage gain as obtained from
the simulation. Readers are encouraged
to make sense of the waveforms
for the PMOS source follower.
To find the output resistance of
the source follower, we look into the
source of the transistor (while its
gate is grounded), and we see a smallsignal
resistance of /gr1
me o
<
(a)
(b)
FIGURE 2: Two implementations of a voltage buffer, also known as a source follower, using
(a) an NMOS transistor and (b) a PMOS transistor.
200 mV
0.2
0.4
0.6
0.8
1
05 10 15 20 25
Time (ns)
(a)
vin
520 mV
140 mV
vout
0.2
0.4
0.6
0.8
1
05 10 15 20 25
Time (ns)
(b)
FIGURE 3: A pair of input and output waveforms of (a) an NMOS source follower and
(b) a PMOS source follower.
TABLE 1. THE NMOS AND PMOS PARAMETERS CORRESPONDING TO TWO
SIMULATED SOURCE FOLLOWERS.
PARAMETER
W/L
| VT
gm
gmb
ro
|
NMOS
400 nm / 45 nm
0.43 V
0.5 mS
0.15 mS
11.15 kX
PMOS
1,150 nm / 45 nm
0.35 V
0.47 mS
0.13 mS
9.5 kX
The W/L values are chosen such that the two transistors have a comparable gm
14 SUMMER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
.
[1].
This resistance, which is around
.Ω
14k for our two circuits, based
on the numbers in Table 1,
is cer140
mV
520 mV
200 mV
vin
vout
tainly a considerable deviation from
the ideal value of zero. However,
this deviation finds relevance only
in relation to the load resistance. If
the load resistance is much larger
than .Ω,14k then our source follower
and the ideal voltage buffer
would act similarly. In a sense, the
output resistance of the source follower
determines a lower bound on
the load resistance, below which the
deviation from the ideal voltage buffer
would become unacceptable. In
our case, for load resistances above
14 Ω,k the voltage gain will never
drop below 0.9 V/V, and this may
be acceptable to us. However, if we
wish to drive a load resistance of
.Ω
14k or less, the voltage gain will
drop to below 0.5 V/V, which may
be unacceptable.
Figure 4 shows the dc characteristics
of the two source followers
and compares them against that of
an ideal voltage follower. We distinguish
two clear deviations here:
■ The range of the input voltage over
which either the NMOS or the PMOS
source follower operates properly
Volts
Volts
IEEE Solid-States Circuits Magazine - Summer 2022

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