IEEE Solid-States Circuits Magazine - Summer 2022 - 31

Iv, sourced by MCS and by a new device,
MM, respectively. If is designed
to contribute to most of the desired
Iu, let's say, .,
II just as an
fu
+ 08 F
example, while Iv is going to make
up for the difference to realize the
full Iu =If + Iv. Both MCS and MM are affected
by mismatch, but while MCS's
biasing is fixed, the calibration acts
to control MM's current so that the
resulting Iu is controlled to be equal
to a desired reference value IREF with
high accuracy. During this calibration
phase, the digital signal Cal is
high. This turns on the PMOS switch
that shorts MM's gate with its drain; it
also turns on a switch connecting the
reference current IREF to the drains
of MCS and MM; finally, MCAS and the
current-steering switches are disconnected
from the tail source by
another switch controlled by Cal.
This current cell is effectively disconnected
from the rest of the DAC.
Also, in this " calibration mode, " MM
is diode connected. And because Iu
must be equal to IREF, then MM's current
Iv is forced to settle on a value
that compensates for all mismatches
in MM and MCAS. MM's gate-source
voltage VgsM settles on whichever
value supports this corrective
drain current. Once this is settled,
the calibrated current source can
be reconnected to the rest of the
DAC for regular operation: Cal goes
low, which disconnects IREF, opens
the PMOS switch that was diodeconnecting
MM, closes the switch
at MCAS's source, and the current
cell is ready for regular operation
again. Something very interesting
just happened as Cal turned low
and the PMOS switch tied to MM's
gate opened: at this time, MM's gate
capacitance CM stored the previously
settled calibration VgsM, just
like a switch-capacitor sample and
hold circuit would sample an input
signal. This voltage VgsM is held in
place and continues supporting
the corrective Iv. This two-device
subcircuit is the simplest form of
a so-called current copier, which
in this example is tantamount to a
local analog memory storying the
amount of current required by the
calibration [17].
Indeed, many nonidealities should
be accounted for, such as charge injection
from the PMOS switch into
CM, careful timing of the opening and
closing of all switches, or preserving
the voltage of various floating nodes
during this sequence of steps. There
are well-known remedies for each of
these issues [17], and I do not digress
to discuss them here. Also, it's important
to remember that Iv contributes
a minor amount to Iu: the correction
for what should be a small mismatch
among unit currents Iu. Hence,
a small analog error on Iv is a much
smaller error on Iu, particularly when
compared to its uncalibrated value.
However, a few more points matter.
First, a single-reference IREF current
is used to equate all cells in the
DAC array. Second, as the cell that is
calibrated must be disconnected from
the others, an additional ( " spare " )
precalibrated cell
is required to replace
it if we run the calibration in
background. In this case, calibration
cycles through all the required cells
of the DAC, disconnecting them and
calibrating them, one at a time, while
all others are connected to the output
nodes and operate regularly. So,
each local analog calibration memory
is periodically refreshed to catch up
with any drift that might have occurred
since the last calibration cycle.
One drift that requires a periodic VgsM
refresh is the droop on this voltage
slowly occurring because of charge
leak on CM, due, e.g., to the reversebiased
source/bulk junction of the
PMOS switch at MM's gate or through
tunneling current across MM's gate
itself [2], [16]. Extensions of this idea
have been made. These comprise calibration
of the complete stack, including
the cascode transistors, as well as
removing some of the series switches
for better headroom, removal of disturbances,
and so on [18], [19].
To mitigate all of these and other
problems, a possible solution consists
of replacing the current copier
and its analog correction with a
mixed-signal loop, as shown in Figure
9(b) [20]. In that, a very small calibration
DAC supplies the correction
current Iv. Few bits provide enough
accuracy for the cal-DAC's correction
current. These bits are stored
in a small, local RAM. Each current
source has its own dedicated calDAC
and RAM. To complete the calibration
loop, a single-calibration
ADC and single-reference current
IREF are time-multiplexed through
the calibrated array to determine
and store each individual RAM with
the respective value needed to generate
Iv such that each Iu is forced to
be equal to IREF. The previous analog
loop of Figure 9(a) set VgsM's, while
this new loop in Figure 9(b) sets the
MCS MM
VCS
If
Iv Cal.
Cal.
IREF
MCAS
c0+
Cal.
Cal.
VCAS
c0-
MCAS
c0+
(a)
c0-
(b)
FIGURE 9: Current calibration (a) with current copiers and (b) with local calibration DACs.
Cal. calibration.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2022
31
Cal.
VCAS
IREF
MCS
VCS
If
Iv
CALADC
CALDAC
RAM
CM

IEEE Solid-States Circuits Magazine - Summer 2022

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