IEEE Solid-States Circuits Magazine - Summer 2022 - 33

The first mechanism of nonlinear
distortion is due to the output
swing vout itself. For any cell, one of
the two steering switches is turned
on: during this on time, versus has
a quiescent voltage determined by
the corresponding on switch, while
the dynamic voltage corresponds
to a copy of the respective dynamic
output node voltage, attenuated by
combination of the intrinsic gain of
the on switch and its output cascode
device Mc. It can be proven that this
output modulation of versus mainly
contributes to the third-order distortion
on vout. The only mitigation
consists of maximizing attenuation
through the switch and Mc.
This mechanism is substantially
negligible if the DAC's output current
iout is injected into a very low impedance
node, such as the input virtual
ground of a transimpedance stage
constituting the next (filtering) stage
of a communication systems transmit
signal chain as the voltage swing on
the switches' drains is very limited.
As the switches change state,
steering their tail currents from one
output node to the other, another
nonlinear distortion mechanism occurs.
As depicted in Figure 10(a),
once the latch, with back-to-back inverters,
changes the state of control
signals c0+/c0, versus can experience
a nonnegligible transient. The latter
occurs only on those cells changing
state when the clock clk goes up:
this depends on which code Din(j)
was converted before this time and
which code Din(j + 1) is about to be
converted after that. All other cells
do not experience any change. As
these transients only happen to some
specific cells, depending on the code,
then nonlinear distortion occurs. For
the affected cells, the transient primarily
consists of charging the Cgs of
the switch that is turned on, while simultaneously
discharging the Cgs of
the switch that is turned off. Ideally,
for a perfectly balanced transition of
c0+/c0, the output's common mode of
the latch should match the input's
common mode of the steering pair
and stay constant during transition:
Sometimes, CML is used to interface latches
and steering pairs.
the rising/falling edges of c0+/c0−
should time align to ensure that no
disturbance to the common mode is
experienced. Additionally, in this ideal
scenario, there should be no MOS
switch mismatch introducing offsets
to the resulting redirection of Iu toward
the right output node. Finally,
the low and high voltage levels of the
latch should be just right to ensure
that all Iu is steered from one output
leg to the other, without overdriving
the transfer characteristic of this differential
pair or pushing any device
away from saturation.
As the reader has already guessed,
nearly all of these assumptions are
practically very hard to meet with a
circuit like the one in Figure 10(a), particularly
if the inverters are traditional
CMOS inverters. Actual implementations
require introducing appropriate
level shifters between the digital
latch and the steering pair to set suitable
levels and edges for c0+/c0−, meeting
the steering pair's requirements
and meeting the voltage compliance of
the output nodes' swing levels so the
+- Vout
q0
c0+
vS
c0-
q0
Iu
(a)
VDDA
VDDA
Iu
c0+
+-
Vout
(b)
FIGURE 10: Driving the steering pairs (a) using a direct back-to-back latch and (b) using
separate supplies to fit the stack biasing.
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2022
33
c0-
Latch
VDDD
c0CM
c0-
c0+
VDDD
clk
q0
q0
clk
c0-
c0+
on switch stays in saturation while the
output vout+/vout− swings at its drain.
Sometimes, CML is used to interface
latches and steering pairs.
Things are slightly easier in the
case of the circuit shown in Figure
10(b), where a lower supply VDDD
is employed for the switch drivers,
while the steering pair can be powered
with a higher analog supply
VDDA. The output swing may still be
relatively headroom limited though.
As mentioned earlier, even when
the switch control levels c0+/c0−
and their transition edges ensure
a minimal disturbance on versus,
output nonlinear distortion is still
introduced because, depending on
the present and the next Din, some
cells change their state while others
do not. Hence, some versus are
disturbed by the charging and discharging
of a switch's capacitances,
while others are not. This code dependency
can be removed by replacing
the dual-switch topology
presented in Figure 11(a) with an
extension known as a quad-switch
IEEE Solid-States Circuits Magazine - Summer 2022

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