each complete steering cell, along with minimal local logic, over a 2D array [5]. This alternate floorplan, sometimes known as Manhattan style, has gradually become unpopular for very high sample-rate DACs. Although it helps minimize strays within the individual cell, it does particularly poorly with nearly all the architecture-level challenges covered thus far, which are often dominant with increasing frequency and sample rate. Timing Skews Among Cells As discussed in previous sections, static current mismatch among nominally identical cells introduces error patterns that mix with the intended output signal synthesis, causing static nonlinear distortion. Similarly, multiple other nonidealities cause the time at which each cell changes state to have errors with respect to when it should change state: mismatches in time among the cells create timing skews with respect to an ideal common time base. Error-pattern-mixing mechanisms