Multiband RF Sampling ADC Digital Down Converter Q1 N Decimation Filter I1 N Digital Down Converter Q2 Signal1 N Decimation Filter I2 N (a) FIGURE 11: (a) A block diagram schematic of a multiband RF-sampling ADC and (b) an example multiband digital down conversion. products existing between the different channels. Pipelined and Interleaved High-Speed ADCs Direct sampling at the RF is generally impractical because power consumption increases as a function of the sampling frequency, f .S This is largely because switching operations consume power proportional to the switching speed, and generating clocks with low jitter and distribution and buffering also require substantial power [22]. Time interleaving uses a combination of M ADCs operating at an effective sampling rate of /fMS as shown in Figure 12. In principle, each of the M sub-ADCs and the clocking are easier to design since they are not operating near the limits of the technology. However, this does not necessarily result in power savings because though each of the subADCs ostensibly operates with a factor of M less power, there are M sub-ADCs. In reality, the need for precision multiphase clocking and precise sample alignment requires additional overhead power. Increasing the number of interleaved subADCs results in increased complexity and typically higher overhead power [23]. In a pipelined ADC, the data conversion is broken down into a series of sub-ADCs that each operate at a lower resolution, also intending to relax the NCO2 sin cos fs Frequency (Hz) (b) Signal2 NCO1 sin cos ADC Filter LNA ADC4 Signal Input ADC2 ADC1 Clock (fs) fs/4 Quadrature Clock Generator 0° 90° 180° 270° (a) Clock Input 0° Clock 90° Clock 180° Clock 270° Clock (b) FIGURE 12: (a) A block diagram schematic of a time-interleaved ADC and (b) an example interleaved sampling operation. IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2022 61 Sample Alignment Signal Output ADC3 Relative Power (dB)