IEEE Solid-States Circuits Magazine - Summer 2022 - 73

121 TOPS/W and a MAC compute density
of 2.67 TOPS/mm2 are reported.
In [47], a 28-nm programmable
IMC accelerator chip with 20 mm2
has been presented. Using a capacitive
coupling-based SRAM IMC bitcell,
a 256 × 128 SRAM IMC macro
is designed with a column-parallel
4-b ADC, and 108 such macros are
integrated for the total chip. A total
of 3.4 Mb of memory was dedicated
for SRAM IMC, and 1.5 Mb of off-theshelf
activation memory was also
employed. A custom instruction set
architecture (ISA) was developed
for programmability support with
IMC and SIMD operations, where
the hardware loop control feature
was able to reduce the total number
of instructions by 4×. A peak
system-level energy efficiency of
437 TOPS/W and peak throughput
of 4.9 TOPS for binary precision
were demonstrated. These energy
numbers include all components of
the overall accelerator chip, such
as the activation memory, 256-way
SIMD unit for vector operations, and
on-chip communication.
The recent trends of analog/
mixed-signal AI accelerators can be
summarized as follows:
■ Many single-macro IMC designs
have been presented in recent
years, and, currently, the best IMC
designs report >1,000 TOPS/W at
the single-macro level [49], [50].
Both resistive IMC and capacitive
IMC have been demonstrated,
where capacitive IMC shows higher
linearity between MAC results
and analog voltage values.
■ Analog IMC designs also support
multibit and flexible precision
from 1- to 8-b precision for both
activations and weights of DNNs
[33], [35], [38], [39], [50], [51]. Some
sparsity-aware IMC designs have
also been presented [16], [52] to
further optimize energy with
techniques such as zero skipping.
■ More recently, larger-scale IMC
accelerators that integrate more
than 100 IMC macros have been
recently reported in scaled CMOS
technologies, where several megabits
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2022
73
Bitwise Multiplication Implementation:
Capacitor Charge or Discharge
MAC Computation Mechanism:
WL
Capacitive
IMC [40]
Valavi et al.,
JSSC 2019
IAbx,y,z
M6
M8
M1
Wi,j,k
n
BL
Drive Vc With Zero or One
BL
WL
Capacitive IMC:
C3SRAM [43]
" C3SRAM "
Jiang et al.,
JSSC 2020
MWL
Cc
(a)
Q
Vc
QB
MBL
MWLB
6T
MWL[n]
MWLB[n]
(b)
Capacitive Divider
M2
Wbi,j,k
n
BLb
6T
BLB
MWL[1]
MWLB[1]
6T
MWL[2]
MWLB[2]
MBL
VSS
a
MBL
N-a
Capacitive Coupling
VDD
M3
M4
M5
M7
IAx,y,z
Oi,j,k
n
Broadcast
Input
Activations
IAx,y,z
Multiplying Bitcell
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Measured Transfer
Function
Charge Loss due
to Wire Parasitics
Shallower Slope due to
Charge Sharing With
ADC Input Capacitors
-256 -128
(c)
FIGURE 6: The capacitive IMC circuits and operation. (a) the IMC SRAM bitcell design, (b) N bitcells connected to the same RBL, and (c) the N-input MAC computation. MWL and MWLB represent
differential MAC wordlines. HL: hidden layer.
128 256
MAC Value
Self-Calibrated
-3 × 3 × 512
3 × 3 × 5
HL Preactivation (PAx,y,n) Value
Charge Sharing
Neuron Tile
Neuron
Patch
60
Error bars show sigma
IEEE Solid-States Circuits Magazine - Summer 2022

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