IEEE Solid-States Circuits Magazine - Summer 2022 - 75

IMC is not particularly amenable for
fine-grain weight pruning. Here, we
introduce specific approaches that
have been proposed to tackle each
of these challenges.
Addressing a Low SNR
Associated with a lower SNR, analog
IMC involves inherent intrachip
and interchip variability as well as
ADC quantization. As shown in a
number of IMC chips from the literature,
variability can be observed in
the ADC outputs for the same ideal
MAC value, and accuracy degradation
is often reported compared
to the digital baseline. To mitigate
this accuracy loss, some IMC SRAM
works attempted to improve the SNR
by limiting the number of activated
rows for IMC, e.g., 18 rows in [38],
but this reduces the computing parallelism
and energy efficiency.
To improve the IMC hardware
accuracy, recent works, such as [54],
performed customized DNN training
with noise injection at the individual
weight level, where the injected noise
is drawn from Gaussian distributions
based on memory bitcell variations.
However, such individual weightlevel
Gaussian noise injections could
be suboptimal for actual IMC chips
for two reasons: 1) individual weightlevel
noise does not consider the IMC
crossbar structure and other hardware
noise, such as bitline or ADC
noise, and 2) Gaussian noise does not
necessarily represent the actual IMC
hardware noise well [55].
Considering these, IMC noiseaware
DNN training is performed
[55] by injecting the measured IMC
hardware noise into the forward pass
during DNN training. All MAC operations
in DNNs are divided into multiple
N-input MAC operations, where
N is the number of rows activated
together in the IMC macro. For each
N-input MAC operation, the noisy and
quantized partial sum results from
IMC chip measurements are used,
where the ADC outputs for given MAC
values are randomly sampled based
on the conditional probability of ADC
output measurements for each MAC
We need ADCs and DACs because we perform
analog computation inside the IMC macro while
utilizing digital activation storage and digital
communication between IMC macros.
value. In [55], injecting actual IMC
hardware noise measured from two
different IMC chips of XNOR SRAM
[42] and C3SRAM [43] has been evaluated.
The reported results show that
the IMC noise-aware training scheme
shows higher inference accuracy for
the IMC hardware across multiple
DNN models, different precision, and
a different amount of noise, and the
improvement is especially higher for
higher-noise environments (e.g., a
low Vdd for C3SRAM [43]).
Addressing Area-/
Energy-Hungry ADCs
Why are relatively high-resolution
ADCs necessary for IMC? Each IMC
macro has a finite number of rows
(e.g., 256), which computes the partial
sums of a DNN layer. When dividing
a large dot product into a number
of smaller ones, each partial sum
should not be prematurely quantized
and should have relatively high precision.
With regard to the ADC challenge,
different methods have been
proposed for possibly removing the
ADCs (and DACs) for IMC designs.
We need ADCs and DACs because we
perform analog computation inside
the IMC macro while utilizing digital
activation storage and digital communication
between IMC macros.
Then, we can think again about 1) an
all-digital design but with IMC and 2)
an all-analog AI accelerator where all
operations are performed in the analog
domain.
Digital IMC
All-digital IMC designs were recently
presented in [56] and [58] [Figure 9(a)].
In analog IMC, the bitwise multiplication
results are accumulated in
an analog manner along the bitline,
which then necessitates an ADC at
the column end. On the other hand,
the digital
IMC design proposes
performing the accumulation with
Energy Efficiency Versus Throughput for SRAM, eNVM, and Digital
104
103
102
101
10-3
10-2
10-1
100
101
1-b TOPS
FIGURE 8: The digital and analog accelerator literature. (Adapted from [48].)
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2022
75
SRAM IMC Macro
SRAM IMC System
eNVM IMC
Digital
102
103
104
1-b TOPS/W
IEEE Solid-States Circuits Magazine - Summer 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2022
