IEEE Solid-States Circuits Magazine - Summer 2023 - 13

you to sniff out the weakness and
fix it. However, not all mechanisms
are straightforward.
The most common pitfall involves
In Figure 4(a), a
Miller integrators.
common op-amp topology with a
PMOS high-gain stage illustrates what
can go wrong. Notice that everything
below the dashed line looks like a
current source to the top part of the
circuit. This leaves the PMOS transistors
free to move up and down
with VDD. That's OK...except for
the Miller compensation capacitor,
Cmiller. This capacitance wants to
drag the output node up and down
with VDD too. Think of it this way:
at high frequencies, Cmiller effectively
shorts M_HUGE's drain to its
gate, making M_HUGE into a diode,
and couples VDD noise directly to
the output. (A feedforward blocking
resistor in series with Cc may offer
some improvement, but it does not
eliminate the problem.)
If this topology had been upside
down, i.e., NMOS current mirror
and integrator, then all this would
not have been a problem. That's
because we normally evaluate the
output relative to ground. (See " Is
Ground Different? " ) If everything
moves up and down with ground,
that's perfect. (This is not true for
stand-alone op-amps, which have a
separate negative supply that is not
ground [1].) So, it's generally better
to stick with NMOS
implementation
unless the load is referenced to
VDD. But in some cases, there just
is no option, like in a low-dropout
regulator (LDO). In those situations,
refer to Figure 4(b) for the fix.
This elegant solution comes from
my colleague Jack Kenney at Analog
Devices. (Unfortunately, I've been
obliged to strip off many of the cool
details of his masterpiece to make
the main point clear.) In Figure 4(b),
cascodes have been added to the
input stage. Importantly, the cascodes
are referenced to ground. One
of these forms the return point for
the feedback current through the
compensation capacitor.
Frequency compensation like
this is sometimes called " indirect "
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2023
13
because the feedback does not connect
directly to the input of the second
stage. One of the primary missions
of indirect compensation is to make
the feedback more unidirectional and
block the feedforward path found
in standard Miller compensation,
thus eliminating a
pesky RHP zero. But it also
makes more efficient use
of the feedback capacitance,
resulting in less
area or higher speed.
Indeed, some people
believe you'd be nuts to
use any other kind of
compensation [2].
For the purposes of Figure 4(b),
(which is often the minimum length
to get good transconductance).
The two current sources, IC1 and IC2
in Figure 4(b) may not be needed in all
situations, but they can be included
to lower the impedance of the cascode
nodes and improve
the frequency response.
Now, when things
go wrong, the
fault is usually
not with the
simulator; it's
that we asked
it the wrong
question.
(The zero formed by
MC2 source impedance
and Cmiller is the issue.)
These currents also help
to keep the cascodes alive
during slewing.
Although the current
mirror must be PMOS to be
compatible with the PMOS
however, the big advantage of indirect
feedback is the ground (rather
than VDD) referenced feedback
point for Cmiller. Now VDD cannot
reach through to the output, and the
PSRR is much improved. Of course,
the feedback path could be through
a dedicated path instead of cascodes
[3]. But the cascodes also provide
VDD protection for the input pair
pass device, M_HUGE, the presence
of the cascodes allows the option
of a PMOS differential pair folded
cascode with very little impact on
the design. If the current source
feeding a PMOS differential pair is
stiff enough, the input pair does not
need protection from VDD as in the
NMOS case.
Finally, if you cut Figure 4(b)
along the dotted line, you'll see that
IS GROUND DIFFERENT?
No, not really. GND is fundamentally no different from VDD. You might say that ground is just
another power supply with better PR. However, in practice, it is usually treated very differently.
First of all, we usually express all voltages as referred to the local ground potential, the primary
exception being differential signals. Voltages are always difference measurements, so some
reference level is required. We call that ground. This has a profound impact on how we think
about PSRR. If there is a disturbance on ground, we want the signal voltage to follow it, so the
signal-to-ground voltage is not corrupted. In other words, we want exactly 0 dB of PSRR from
the local ground rail to the signal. (As an aside, an interesting example of this philosophy can
be found in standard emitter coupled logic, or ECL, in which the positive supply is ground. The
only other supply is negative. This is because all signals are generated by NPNs driving resistors
attached to the positive supply, hence ground.)
There was a time when it was popular to provide a dirty, heavy-duty " power ground " to
handle all of the supply currents and a clean, but often fragile, " signal ground " to act as a
universal reference potential. That practice is not so common anymore, and a single ground
usually fills both roles. To handle the currents, this " common ground " must be a wide trace or
power plane, which is good for absorbing high-speed transients and simultaneously insuring a
relatively constant reference potential across the chip.
While you may still see an " analog ground " that is separate from the " digital ground, " it is
unusual to see the same proliferation of ground planes that happens with positive supplies.
Because different supply voltages are required, or because the designer wishes to isolate a
particular block (which is not a strategy I endorse, by the way), there can be quite a few positive
supply nets on a chip. This leads to thin, " fingery " metal runs on the die or the carrier laminate
that are highly inductive and resistive compared with the wide solid planes that are instinctively
used for ground. So, in practice, GND is often different from VDD.

IEEE Solid-States Circuits Magazine - Summer 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2023