IEEE Solid-States Circuits Magazine - Summer 2023 - 19

Appendix: Related Articles
[A1] C. Auth and A. Shankar, " Evolution of transistors:
Humble beginnings to the ubiquitous
present, " IEEE Solid-State Circuits
Mag., vol. 15, no. 3, pp. 20-28, Summer
2023, doi: 10.1109/MSSC.2023.3281538.
[A2] L. W. Nagel and C. C. McAndrew, " The
evolution of transistor models: Always
trying to keep up with the evolution
of transistors, " IEEE Solid-State Circuits
Mag., vol. 15, no. 3, pp. 29-35, Summer
2023, doi: 10.1109/MSSC.2023.
3284805.
[A3] M. Ikeda, " Reflections on progress in digital
circuits: From basics to untangle past
trials, " IEEE Solid-State Circuits Mag., vol.
15, no. 3, pp. 36-42, Summer 2023, doi:
10.1109/MSSC.2023.3290099.
[A4] Y. Chae, C. M. Lopez, K. A. A. Makinwa, M.
Ortmanns, and W. Sansen, " A glimpse of the
history of analog ICs, " IEEE Solid-State Circuits
Mag., vol. 15, no. 3, pp. 43-52, Summer
2023, doi: 10.1109/MSSC.2023.3282557.
[A5] T.-Y. J. Chang, F. Hamzaoglu, Y. Li, K.
Sohn, Y. Wang, and J. Wuu, " A trip down
memory lane: Reflections on the progress
in memories, " IEEE Solid-State Circuits
Mag., vol. 15, no. 3, pp. 53-61, Summer
2023, doi: 10.1109/MSSC.2023.3287169.
[A6] B. Razavi, " 75 years of RF design: Highlights
and paradigm shifts, " IEEE SolidState
Circuits Mag., vol. 15, no. 3, pp. 62-79,
Summer 2023, doi: 10.1109/MSSC.2023.
3280435.
[A7] N. Collaert, " Advancements in IC technologies:
A look toward the future, " IEEE
Solid-State Circuits Mag., vol. 15, no. 3,
pp. 80-86, Summer 2023, doi: 10.1109/
MSSC.2023.3280433.
CIRCUIT INTUITIONS (continued from p. 9)
shows that the output voltage follows
the input voltage, albeit with
a voltage drop v ,1GS
shown in Figure
6(b), that can change from 0.4 V
to 0.6 V. Given that the threshold
volt age of M1
T1 . .
to Table 1, when v 1GS
is V 04V according
is close to 0.4 V,
M1 is expected to turn off and not
conduct any current. This is indeed
consistent with the current waveform
of i 1DS
Interestingly, each of M2
shown in black in Figure 6(c).
and M3
also experience time intervals during
which they contribute zero current to
the output load; i 2SD
in green is near
zero in the (0.3-ns, 0.4-ns) time interval,
and i 3SD
(0.5-ns, 0.6-ns) time interval.
Given that the total load current
iL can be written as the sum of
the three transistor currents, i.e.,
ii ,
SD SD
DS123i++ we can see how the
three transistors cooperate to provide
the total current to the load.
The notation
i 2SD , for example, represents
the total current from source
to drain in M2
. When the maximum
positive current is being delivered
to the load, transistors M1
and M2
join forces to supply the required
current to the load, while transistor
M3
is off contributing zero current
to the load. On the other hand, the
maximum negative current is delivered
to the load by M3
alone as both
M1 and M2
conduct almost zero curin
red is near zero in the
will
rents at this time. There is an interval,
however,
around t .,=045ns
during which all transistors are
on and contribute currents to the
load. This happens around the time
when the input signal deviates only
slightly from its bias value and all
transistors conduct current to perform
what is referred to as class A
operation. At other times, only one
or two transistors among the three
source/sink current to the load, and
the other one or two transistors are
off. This is referred to as a class AB
operation when each transistor conducts
currents only for a portion
(more than half) of the period and
stops conducting current for the
remaining portion. By superimposing
ii
DS12SD
+
and ii curves
curve,
DS13SD
+
on top of the load current iL
Figure 6(d) clearly shows how iL
constructed by ii around its
peak (when SD3 0. by the ii
curve around its trough (when iSD2 0. ),
and by ii i123DS ++ in other parts
is
DS12SD
+
i
),
SD SD
where all three transistors conduct
current.
In summary, we have shown that
the SVF, the FVF, the SSF, and the
AB-SSF all offer the same voltage
gain of around 0.7 V/V. The main
advantage of the FVF, SSF, and ABSSF
over the SVF is their reduced
output resistance, which is a major
improvement in the design of a
DS13SD
+
voltage follower. Among the four
designs, the AB-SSF exhibits the lowest
output resistance and a much
better symmetric slew behavior in
its output voltage thanks to its class
AB operation.
Acknowledgment
Many thanks to Jhoan Salinas for
his assistance with the simulation
results in this article.
References
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IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2023
19
http://dx.doi.org/10.1109/MSSC.2022.3182791 http://dx.doi.org/10.1109/TCSI.2005.851387 http://dx.doi.org/10.1109/TCSI.2005.851387 http://dx.doi.org/10.1002/cta.776 http://dx.doi.org/10.1109/MSSC.2014.2315062
IEEE Solid-States Circuits Magazine - Summer 2023

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