IEEE Solid-States Circuits Magazine - Summer 2023 - 24

While the short-channel benefit of FinFETs was
appealing, the process challenges with FinFETs
deterred all but the most daring device engineers.
to a plethora of layout-dependent effects
that impacted designers. This
has led to pre- to postlayout simulation
gaps resulting in design iterations
[19], [20]. The breakthrough of
adding uniaxial strain enabled additional
scaling [21], [22] but the challenges
of scaling remained at the
forefront of technical conversations.
Gate dielectric thickness scaling was
losing steam through 90- and 65-nm
technology nodes. The industry-standard
silicon oxynitride (SiON) gate dielectrics
were simply running out of
atoms. (The industry migrated from
a pure silicon dioxide gate dielectric
to SiON when p+ polysilicon was introduced
in PMOS.) As the gate dielectric
thickness was scaled thinner and
thinner, the gate leakage was growing
exponentially. Meanwhile, depletion
in the polysilicon gate, due to the limited
conductivity of polysilicon, was
also becoming a limiter for inversion
gate oxide thickness reduction. Significant
resources had been dedicated
to the research of alternative high
permittivity or Hi-k dielectrics to use
for the gate dielectric. A Hi-k dielectric
enables the use of a thicker gate
dielectric to significantly suppress
tunneling leakage while maintaining
and/or improving gate coupling to
the channel. But the degradation of
mobility in the channel with the introduction
of the Hi-k dielectric was a
significant stumbling block.
Even strain engineering was seeing
the impact of the shrinking gate
pitch. On the NMOS side, as the space
between the gates was shrinking, the
drive current benefit of the strained
tensile capping layer was reduced,
and similarly, on the PMOS side, the
benefit of compressive strain from
the embedded SiGe S/D was shrunk
with the scaling of the pitch.
In the midst of these challenges,
the definition of the 45-nm technology
node began. The first order of
business was to decide on the gate
stack. Leaving the traditional silicon
dioxide gate dielectric with a polysilicon
gate electrode was a daunting
undertaking. The introduction
of silicon dioxide enabled the MOS
transistor to become a reality and
was the foundation of the CMOS process
for >40 years, so there was a
large contingent that was looking for
options to continue to squeak a few
more generations without the largescale
disruption of overhauling the
gate stack. The cupboard was bare,
though, with no promising alternatives
to replacing the gate stack. The
question that plagued the community
was what challenge to embark on
first-replace the gate dielectric with
a Hi-k material or replace the polysilicon
gate with a highly conductive
metal gate.
Instead of choosing one or the
100
10
1
0.1
0.01
0.001
0.0001
0.00001
SiON/Poly 65 nm
>25×
~1,000×
SiON/Poly 65 nm
other, the industry decided to dive
into both at once. Significant progress
had taken place in the understanding
of Hi-k and metal-gate
stacks over the preceding five years
(Figure 4). The degraded mobility
and reliability from Hi-k gate
dielectrics were resolved by combining
the Hi-k gate dielectric with
a metal gate. One major problem
was solved, but the introduction of
metal gates along with Hi-k introduced
several new issues. Two workfunction
metals would be needed to
support both NMOS and PMOS devices,
and a high-conductivity bulk
metal material would be needed. The
new gate stack would also need to be
compatible with the uniaxial strain
performance enhancement that had
been so successful over the past two
generations. Looking at this list of
challenges, it would be easy to wonder
if it was worth leaving SiON +
polysilicon gates, but the gate leakage
benefit was a compelling −25×
on NMOS and an astounding 1,000×
on PMOS. The verdict from the data
was loud and clear.
In the development of a metal-gate
Hi-k + MG 45 nm
PMOS
-1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2
VGS (V)
Hi-k + MG 45 nm
NMOS
0.4 0.6 0.8 1 1.2
FIGURE 4: Hi-K + metal gate provided >25× reduction in leakage on NMOS and ~1,000×
reduction in leakage on PMOS. MG: metal gate; Poly: polysilicon; VGS: gate-to-source voltage.
(Source: Adapted from [23].)
24 SUMMER 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
process flow, there were two front
runners. One was called gate first.
This was similar to the existing flow
with the SiON gate dielectric swapped
for a Hi-k gate dielectric stack of
SiO2+HfO2, and the polysilicon gate
was replaced with a metal-gate stack
that had two different work-function
metal layers. While this provided a
familiar look and feel to the traditional
flow, it introduced constraints
on thermal processing for S/D epitaxy
and dopant activation, and it
Normalized Gate Leakage

IEEE Solid-States Circuits Magazine - Summer 2023

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