IEEE Solid-States Circuits Magazine - Summer 2023 - 51

[10] B. Verbruggen et al., " A 70 dB SNDR 200
MS/s 2.3 mW dynamic pipelined SAR ADC
in 28nm digital CMOS, " in Proc. Symp.
VLSI Circuits Dig. Tech. Papers, Honolulu,
HI, USA, 2014, pp. 1-2, doi: 10.1109/VLSIC
.2014.6858451.
[11] M. S. Akter, K. A. A. Makinwa, and K.
Bult, " A capacitively degenerated 100-dB
linear 20-150 MS/s dynamic amplifier, "
IEEE J. Solid-State Circuits, vol. 53, no. 4,
pp. 1115-1126, Apr. 2018, doi: 10.1109/
JSSC.2017.2778277.
[12] F. Krummenacher, E. Vittoz, and M. Degrauwe,
" Class AB CMOS amplifier micropower
SC filters, " Electron. Lett., vol.
17, no. 13, pp. 433-434, Jun. 1981,
doi: 10.1049/el:19810304.
[13] Y. Chae and G. Han, " Low voltage, low
power, inverter-based switched-capacitor
delta-sigma modulator, " IEEE J. Solid-State
Circuits, vol. 44, no. 2, pp. 458-472, Feb.
2009, doi: 10.1109/JSSC.2008.2010973.
[14] B. Hershberg, S. Weaver, K. Sobue, S.
Takeuchi, K. Hamashita, and U.-K. Moon,
" Ring amplifiers for switched capacitor
circuits, " IEEE J. Solid-State Circuits,
vol. 47, no. 12, pp. 2928-2942, Dec. 2012,
doi: 10.1109/JSSC.2012.2217865.
[15] R. A. R. van der Zee and E. A. J. M. van
Tuijl, " A power-efficient audio amplifier
combining switching and linear
techniques, " IEEE J. Solid-State Circuits,
vol. 34, no. 7, pp. 985-991, Jul. 1999, doi:
10.1109/4.772414.
[16] W. Kester, Ed., The Data Conversion Handbook.
Oxford, U.K.: Analog Devices, 2004.
[17] B. K. Howard, " Binary quantizer, " U.S.
Patent 2 715 678, 1955.
[18] H. Inose, Y. Yasuda, and J. Murakami, " A
telemetering system by code modulation:
∆-Σ modulation, " IRE Trans. Space
Electron. Telemetry, vol. SET-8, no. 3, pp.
204-209, Sep. 1962, doi: 10.1109/IRETSET.1962.5008839.
[19]
H. R. Kaiser et al., " High-speed electronic
analogue-to-digital
converter
U.S. Patent 2 784 396, Mar. 1957.
[20] R. van de Plassche and R. E. J. van
Der Grift, " A five-digit analog-digital converter, "
IEEE J. Solid-State Circuits, vol.
12, no. 6, pp. 656-662, Dec. 1977, doi:
10.1109/JSSC.1977.1050975.
[21] P. Brokaw, " A monolithic 10-bit A/D
using I2L and LWT thin-film resistors, "
IEEE J. Solid-State Circuits, vol. 13, no.
6, pp. 736-745, Dec. 1978, doi: 10.1109/
JSSC.1978.1052044.
[22] W. C. Black and D. A. Hodges, " Timeinterleaved
converter arrays, " IEEE J. SolidState
Circuits, vol. 15, no. 6, pp. 1022-1029,
Dec. 1980, doi: 10.1109/JSSC.1980.1051512.
[23] L. Samid, M. Ortmanns, Y. Manoli, and F.
Gerfers, " A new kind of low-power multibit
third order continuous-time lowpass
Σ∆ modulator, " in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), 2002, p. III, doi:
10.1109/ISCAS.2002.1010218.
[24] A. Iwata, N. Sakimura, M. Nagata, and
T. Morie, " An architecture
of DeltaSigma
A-to-D converters using a voltage
controlled oscillator as a multi-bit quantizer, "
in Proc. IEEE Int. Symp. Circuits Syst.
(ISCAS), 1998, pp. 389-392, doi: 10.1109/
ISCAS.1998.704448.
[25] B. Murmann and B. Boser, " A 12-bit 75-MS/
s pipelined ADC using open-loop residue
amplification, " IEEE J. Solid-State Circuits,
vol. 38, no. 12, pp. 2040-2050, Dec. 2003,
doi: 10.1109/JSSC.2003.819167.
[26] R. H. Walden, " Analog-to-digital converter
technology comparison, " in Proc. IEEE
GaAs IC Symp., 1994, pp. 217-219, doi:
10.1109/GAAS.1994.636970.
system, "
[27] R. Schreier and G. Temes, Understanding
Delta-Sigma Data Converters. Hoboken,
NJ, USA: Wiley, 2005.
[28] S. Rabii and B. A. Wooley, " A 1.8-V digital-audio
sigma-delta modulator in 0.8-µm CMOS, "
IEEE J. Solid-State Circuits, vol. 32, no. 6, pp.
783-796, Jun. 1997, doi: 10.1109/4.585245.
[29] B. Murmann. " ADC performance survey
1997-2022. " GitHub. Accessed: Apr. 15,
2023. [Online]. Available: https://github.
com/bmurmann/ADC-survey
[30] B. E. Jonsson, " A/D-converter performance evolution, "
Converter Passion, Aug. 2012. [Online].
Available: https://converterpassion.wordpress.
com/2012/08/26/adc-per formance
-evolution-thermal-figure-of-merit-fom/
[31] E. Stern, " Solid-state sensors for process
control, " in Proc. IEEE Int. Solid-State Circuits
Conf., 1963, pp. 60-61, doi: 10.1109/ISSCC.
1963.1157466.
[32] P. W. Fry, " A silicon MOS magneticfield
transducer of high sensitivity, " in
Proc. IEEE Int. Solid-State Circuits Conf.,
1968, pp. 94-95, doi: 10.1109/ISSCC.
1968.1154603.
[33] R. Melen and J. Meindl, " A transparentelectrode
CCD image sensor, " in Proc.
IEEE Int. Solid-State Circuits Conf., 1973,
pp. 130-131, doi: 10.1109/ISSCC.1973.
1155215.
[34] P. B. Denyer, D. S. Renshaw, G. Wang, M. Y.
Lu, and S. Anderson, " On-chip CMOS sensors
for VLSI imaging systems, " in Proc.
IFIP Trans. VLSI, 1991, p. 10.
[35] R. J. Widlar, " New developments in
IC voltage regulators, " in Proc. IEEE Int.
Solid-State Circuits Conf., 1970, pp. 158-
159, doi: 10.1109/ISSCC.1970.1154790.
[36] R. Dobkin,
" Monolithic temperature
transducer, " in Proc. IEEE Int. Solid-State
Circuits Conf., 1974, pp. 126-127, doi:
10.1109/ISSCC.1974.1155303.
[37] K. E. Peterson, " Silicon as a mechanical
material, " Proc. IEEE, vol. 70, no. 5,
pp. 420-457, May 1982, doi: 10.1109/
PROC.1982.12331.
[38] C. C. Enz and G. C. Temes, " Circuit techniques
for reducing the effects of op-amp
imperfections: Autozeroing, correlated
double sampling, and chopper stabilization, "
Proc. IEEE, vol. 84, no. 11, pp. 1584-
1614, Nov. 1996, doi: 10.1109/5.542410.
[39] K. B. Klaassen, " Digitally controlled absolute
voltage division, " IEEE Trans. Instrum.
Meas., vol. 24, no. 2, pp. 106-112, Jun.
1975, doi: 10.1109/TIM.1975.4314388.
[40] R. J. Van De Plassche, " Dynamic element
matching for high-accuracy monolithic
D/A converters, " IEEE J. Solid-State Circuits,
vol. 11, no. 6, pp. 795-800, Dec.
1976, doi: 10.1109/JSSC.1976.1050820.
[41] R. Poujois and J. Borel, " A low drift fully
integrated MOSFET operational amplifier, "
IEEE J. Solid-State Circuits, vol. 13, no.
4, pp. 499-503, Aug. 1978, doi: 10.1109/
JSSC.1978.1051084.
[42] A. Bakker, K. Thiele, and J. H. Huijsing, " A
CMOS nested-chopper instrumentation
amplifier with 100-nV offset, " IEEE J. Solid-State
Circuits, vol. 35, no. 12, pp. 1877-
1883, Dec. 2000, doi: 10.1109/4.890300.
[43] R. Wu, J. H. Huijsing, and K. A. A. Makinwa,
" A current-feedback instrumentation
amplifier with a gain error reduction
loop and 0.06% untrimmed gain error, "
IEEE J. Solid-State Circuits, vol. 46, no. 12,
pp. 2794-2806, Dec. 2011, doi: 10.1109/
JSSC.2011.2162923.
[44] G. C. M. Meijer, R. van Gelder, V. Nooder,
J. van Drecht, and H. M. M. Kerkvliet, " A
three-terminal intergrated temperature
transducer with microcomputer interfacing, "
Sens. Actuators, vol. 18, no. 2, pp.
195-206, Jun. 1989, doi: 10.1016/02506874(89)87018-0.
[45]
B. Boser and B. Wooley, " The design of
sigma-delta modulation analog-to-digital
converters, " IEEE J. Solid-State Circuits,
vol. 23, no. 6, pp. 1298-1308, Dec. 1988,
doi: 10.1109/4.90025.
[46] K. A. A. Makinwa. " Smart temperature
sensor survey. " Accessed: May 1, 2023.
[Online]. Available: https://ei.ewi.tudelft.
nl/docs/TSensor_survey.xls
[47] G. Chen et al., " Millimeter-scale nearly
perpetual sensor system with stacked
battery and solar cells, " in Proc. IEEE Int.
Solid-State Circuits Conf., 2010, pp. 288-
289, doi: 10.1109/ISSCC.2010.5433921.
[48] K. Jeffrey and V. Parsonnet, " Cardiac
pacing, 1960-1985: A quarter
century
of medical and industrial
innovation, "
Circulation, vol. 97, no. 19, pp. 1978-1991,
May 1998, doi: 10.1161/01.CIR.97.19.1978.
[49] K. D. Wise, J. B. Angell, and A. Starr, " An
integrated-circuit approach to extracellular
microelectrodes, " IEEE Trans. Biomed.
Eng., vol. BME-17, no. 3, pp. 238-247, Jul.
1970, doi: 10.1109/TBME.1970.4502738.
[50] J. Xu, S. Mitra, C. Van Hoof, R. F. Yazicioglu,
and K. A. A. Makinwa, " Active electrodes
for wearable EEG acquisition: Review and
electronics design methodology, " IEEE Rev.
Biomed. Eng., vol. 10, pp. 187-198, Jan.
2017, doi: 10.1109/RBME.2017.2656388.
[51] B. B. Winter and J. G. Webster, " Driven-rightleg
circuit design, " IEEE Trans. Biomed.
Eng., vol. BME-30, no. 1, pp. 62-66, Jan.
1983, doi: 10.1109/TBME.1983.325168.
[52] C. Mora Lopez, " Unraveling the brain with
high-density CMOS neural probes: Tackling
the challenges of neural interfacing, "
IEEE Solid-State Circuits Mag., vol. 11, no.
4, pp. 43-50, Fall 2019, doi: 10.1109/
MSSC.2019.2939338.
[53] S. Wang et al., " A compact quad-shank
CMOS neural probe with 5,120 addressable
recording sites and 384 fully differential
parallel channels, " IEEE Trans.
Biomed. Circuits Syst., vol. 13, no. 6,
pp. 1625-1634, Dec. 2019, doi: 10.1109/
TBCAS.2019.2942450.
[54] R. R. Harrison and C. Charles, " A low-power
low-noise CMOS amplifier for neural
recording applications, " IEEE J. Solid-State
Circuits, vol. 38, no. 6, pp. 958-965, Jun.
2003, doi: 10.1109/JSSC.2003.811979.
[55] K. A. Ng et al., " Implantable neurotechnologies:
A review of integrated circuit
neural amplifiers, " Med. Biol. Eng. Comput.,
vol. 54, no. 1, pp. 45-62, 2016, doi:
10.1007/s11517-015-1431-3.
[56] " Tracking advances in neural recording, "
University of Connecticut, Storrs,
CT, USA. 2023. Accessed: Apr. 27, 2023.
[Online]. Available: https://stevenson.lab.
uconn.edu/scaling/
About the Authors
Youngcheol Chae (ychae@yonsei.
ac.kr) received his B.S., M.S., and
Ph.D. degrees from Yonsei University,
Seoul, South Korea, in 2003, 2005,
and 2009, respectively. During his
Ph.D. studies, he advanced oversampling
data converters through
innovative design techniques, including
inverter-based amplifiers. From
2009 to 2011, he was a postdoctoral
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2023
51
IEEE Solid-States Circuits Magazine - Summer 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2023
