IEEE Solid-States Circuits Magazine - Summer 2023 - 54

10
Layout Optimization With
RDR Rules: 28 nm and Below
130 nm
90 nm
1
65 nm
Tall Cell → Flat Cell
45 nm
HC/HD Cells
0.1
Strained Si
HKMG
FinFET
EUV and
High-Mobility Channel
0.01
1998 2000 2002 2004 2006 2008 2010
Year
FIGURE 1: The scaling of the six-transistor SRAM bitcell area.
a trip down memory lane and provide
a survey of key semiconductor
memory technologies-namely, SRAM,
DRAM, Flash NVM, and emerging
memories-from a 2023 perspective.
SRAM
SRAM has been a fundamental element
in
ICs since the early days
of the semiconductor industry. As
SRAM is fully compatible with logic
process technology, it enables monolithic
integration with logic and
analog circuits while allowing its
performance, power, and area (PPA)
to scale with process technology
advancements. In addition, SRAM's
high-speed and high-endurance attributes
make it an ideal candidate
for cache and register file applications.
Figure 1 shows the scaling of
the six-transistor (6 T) SRAM bitcell
area since the introduction of the
130-nm CMOS process node [4], [5].
The continuous process scaling in
the last two decades, enabled by
innovations in transistor architectures
and new materials [6], has reduced
the area of the SRAM bitcell
by nearly 100 times, from 130-nm to
5-nm technology.
Fundamentally, as shown in Figure 2,
WL
the 6 T SRAM bitcell consists of two
back-to-back inverters for bistable
data storage and two N-type fieldeffect
transistor passgates controlled
by WLs for storage node access.
Writes are typically performed differentially
through the BLs when the
WL is active, overcoming the latched
values, while reads are accomplished
by floating the precharged BLs when
the WL is active, and observing the
resulting BL values.
Growing transistor variation and
nq
q
FIGURE 2: A 6 T SRAM bitcell.
54 SUMMER 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
interconnect parasitics in an SRAM
bitcell from miniaturization have
been the primary challenges in scaling
SRAM bitcell area. As the operating
voltage of SRAM needs to scale
to reduce the power consumption
of large cache memories, it has become
increasingly challenging to
maintain sufficient read and write
margins with the growing impact
2012 2014 2016 2018 2020 2022
28 nm
20 nm
16 nm
10 nm
7 nm
5 nm
New Banking
Structure
Design Solution for FinFET:
16 nm and Below
Design Solution for High-R:
10 nm and Below
Color-Aware Design for Double
Patterning: 20 nm and Below
BL (nBL)
Bitcell Area (log, µm2)
BL

IEEE Solid-States Circuits Magazine - Summer 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2023

Contents
IEEE Solid-States Circuits Magazine - Summer 2023 - Cover1
IEEE Solid-States Circuits Magazine - Summer 2023 - Cover2
IEEE Solid-States Circuits Magazine - Summer 2023 - Contents
IEEE Solid-States Circuits Magazine - Summer 2023 - 2
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