IEEE Solid-States Circuits Magazine - Summer 2023 - 58

NAND Flash has become an important storage
medium, having the potential to become even
more widely adopted through its continued
scaling to higher capacity.
Both types of Flash bitcells have
similar structures and operations,
where the floating gate or chargetrapping
layer stores electrons,
which alters the device's threshold
voltage for memory state differentiation.
The different architectures,
however, make scaling very different.
The dramatic scaling of NAND
has put it into a prominent position
in large storage applications, from
mobile phones to datacenters. On
the other hand, NOR scaling has
been stalled at the sub-20-nm range.
The two architectures also have other
differences. For example, while
NOR can be accessed by byte with
an access time of around 50 ns,
NAND can store only large files with
4-KB to 16-KB page sizes, with an access
time in the 50-µs range.
In the past 23 years, the feature size
of 2D NAND has scaled from 200 nm
down to 15 nm. In addition, the 3D
NAND layer count has increased
from 24 to more than 300 in just the
past nine years. The NAND density,
expressed in terms of gigabits per
square millimeter, has increased
200,000 times in those 23 years.
Applications have expanded as a
result, with the NAND Flash industry
revenue reaching US$60 billion
in 2022.
Aside from physical scaling, NAND
logical scaling has also undergone
a transformation, evolving from single-level
cell to MLC, with 5 b per cell
published in 2023 [17]. The NAND
single-die capacity has grown from
128 Mb in the year 2000 to 2 Tb in
the year 2022. The cost per gigabyte
of memory has been dramatically
reduced, with the average price reducing
20% or more per year. Broad
adoption of NAND started in 2005,
when Apple decided to use NAND instead
of a micro HDD in its iPod. It is
now easy to place 1 TB of NAND memory
into a small package, such as a
microSD card, or universal Flash storage,
or embedded multimedia card
package. An SSD can pack 1-64 TB
into a standard NVM express drive
with hundreds of NAND chips. Even
though NAND is still 1,000 times
slower than DRAM in terms of latency,
it is much faster than HDDs, especially
in random reads.
The transition from 2D to 3D NAND
becomes a must when very limited
electrons are stored in the floating
gate in 15-nm 2D NAND memory cells,
which degrades product reliability severely.
The 3D NAND started in 2012
with the production of the 32-layer
VNAND. Now, chips with more than
230 layers are in production, and
we see layer scaling growing up to
1,000 layers. The 3D NAND technology
has transitioned from lithographylimited
to etch-limited challenges as
the memory hole is etched at a highaspect
ratio with expensive tools, and
multiple decks have been employed
to build taller stacks. Besides adding
more layers, the xy-dimension has
Long Live NAND
1,000
First
Viable
BiCS
Two Tiers
Array Overhead
Reduction
4yyL
4xxL
3xxL
2yyL
2xxL
162 L
100
112 L
96 L
64 L
CnA
Memory
Array
SA/PERI
CuA
(CMOS Next Array) (CMOS Under Array)
Memory
Array
SA/PERI
10
2016
Time
FIGURE 9: The continued NAND scaling. SLC: single-level cell.
58 SUMMER 2023
IEEE SOLID-STATE CIRCUITS MAGAZINE
2032
CbA
(CMOS Above Array)
SA/PERI
Memory
Array
CMOS
Wafer
Memory
Wafer
Cell Pitch Scaling
Logical
Scaling
SLC MLC
TLC QLC
PLC
CMOS Scaling
Multistacking
5xxL
Log (TB/Wafer)
Overhead
Overhead
Overhead
Overhead
Overhead
IEEE Solid-States Circuits Magazine - Summer 2023

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