IEEE Solid-States Circuits Magazine - Summer 2023 - 9

circuits in Figure 2 to determine if
these results make intuitive sense.
A rising input will force the outvin
1
put
node to rise in all three designs.
However, the rate of rise at the output
node, which we called the positive
slew rate, or
BL
SR ,+
is constrained
to /IC for the FVF, irrespective
of the size of the input rise. This is
because the maximum current we
can supply to CL
is limited to IB
in
the FVF. Interestingly, this same constraint
does not exist in either the
SSF or the AB-SSF because, in these
designs, the current supplied to the
load during the rise is provided by
the PMOS transistor M2
, which can
supply currents well above its bias
current level.
Similarly, a falling input will force
the output node to fall in all three
designs. However, the rate of fall at
the output,
IC /BL2
SR ,is
constrained to
in the SSF but not in the FVF
and the AB-SSF, where M2 in FVF and
M3 in AB-SSF can sink currents well
above their bias current levels. With
II 50 ABB
SR+
12 n== in our designs, the
of the FVF is similar to the SRof
the SSF, as can be observed in Figure
4(b). The AB-SSF enjoys the best
of both designs.
To further compare the slew
behavior of the three designs, we
consider a 3-GHz sinusoidal input
voltage waveform with 0.4 Vpp,
as shown in Figure 5(a), and plot its
corresponding simulated output
waveforms in the three designs.
Given that () .( ),
f 3GHz, and assuming a simivftin
02 2r t
=
=
lar waveform at the output, say
() .( ),
out
0142rz0
sin
t
x dtvou dt
=02 fr8
pected maximum rate of change
of the output can be written as
ma (/ ). .
vft=+ the ex -
When this
rate exceeds the slew-rate limit of the
design, the output can no longer track
the input, and its rate will be limited
to the slew rate. This behavior can be
observed in Figure 5(b) where the FVF
and the SSF show slew behaviors during
the output rise and fall, respectively,
whereas the AB-SSF is not affected.
Let us now describe the class
AB operation of the AB-SSF circuit
200
-200
0.2
iL
iDS1 + iSD3
Time (ns)
(d)
FIGURE 6: Voltage and current waveforms of the AB-SSF circuit. (a) Input and output voltage
waveforms, (b) the gate-to-source voltage of M1
M2 (in green), and M3 (in red). (d) The current contributions of M1
and M3
(in red) to the total load current (in blue).
through simulation results. We
apply a 3-GHz sinusoidal voltage
waveform with a 0.4-Vpp swing to
the input node and observe its output
voltage, its output current, and
its transistor currents. Figure 6(a)
(continued on p. 19)
IEEE SOLID-STATE CIRCUITS MAGAZINE
SUMMER 2023
9
. (c) The current waveforms of M1
and M2
(in black),
(in green) and M1
0.6
0.7
sin
with
0.6
0.4
0.5
200
-200
0.2
0.2
0.4
Time (ns)
(b)
iDS1
iSD3
Time (ns)
(c)
iSD2
0.6
0.7
0.6
0.7
1
0.2
vin
0.5
0.4
Time (ns)
(a)
vGS1 = vin - vout
vout
0.6
0.7
(b)
FIGURE 5: The impact of the slew-rate limit on a sinusoidal output waveform at 3 GHz:
(a) A sketch of the input voltage waveform. (b) Simulated ac output voltage waveforms for
the three voltage followers: FVF in red, SSF in green, and AB-SSF in blue.
0.1
-0.1
0.25
vout (ac)
AB-SSF
SSF
FVF
0.5
Time (t/T)
0.25
0.5
(a)
0.75
1
Time (t/T)
0.6
0.8
iDS1 + iSD2
µA
µA
(V)
(V)
(V)
(V)
IEEE Solid-States Circuits Magazine - Summer 2023

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