IEEE Solid-States Circuits Magazine - Winter 2020 - 11

New analog-circuit techniques are enabling
improved performance and reduced power for
temperature sensors, frequency references,
voltage references, and amplifiers.
Communication Systems:
Radio-Frequency Subcommittee
Subcommittee Chair: Piet Wambacq,
IMEC, Leuven, Belgium
ISSCC 2020 features terahertz imaging demonstrators, CMOS power
amplifiers (PAs), and phase-lockedloop (PLL) prototypes. Applications
driving advances in the field of radiofrequency (RF) ICs in silicon technologies include 1) broadband and 5G
communications using massive multiple input/multiple output (MIMO)
and millimeter-wave (mm-wave) technologies, 2) the Internet of Things
(IoT), and 3) sensing and imaging at
sub-mm-wave frequencies.

PLL Synthesizers
Visible highlights are PLLs generating
mm-wave frequency carriers directly
or via on-chip multipliers; synthesizers offering lower integrated jitter
and power consumption (for example, a -250-dB jitter-power FOM);
and wideband, frequency-modulated,
continuous-wave radar-chirp generation. Overall, subsampling PLLs

continue to trend lower in power consumption and integrated timing jitter, with all-digital PLLs continuing to
displace traditional analog designs.
Fractional-N bang-bang, all-digital,
and hybrid fractional-N/integer synthesizers are also demonstrating
continuing innovations in more traditional PLL designs.
The trend in the FOM for PLLs, which
depends on integrated jitter (jitter variance) and power consumption, is illustrated in Figure 6. ISSCC 2020 presents
two fractional-N PLLs with outstanding timing-jitter performance:
1) a 12.8-15.2-GHz digital bang-bang
PLL that realizes 66-fs rms jitter and
performs a 1-GHz hop to within
0.1% of the steady-state frequency
in 18.55 ns
2) a 12.5-GHz fractional-N sampling PLL in 28-nm CMOS that incorporates a digital background
phase-error correction to enable
58-fs integrated jitter (fractional
mode) and 51 fs (operating in integer mode).
The overall FOM for these PLLs is consistent with previous designs, as seen in

1.E+11
ISSCC 1997-2019
Jitter = 1 psrms
Jitter = 0.1 psrms
ISSCC 2020

1.E+10

fin,hf (Hz)

efficiency of this operation is typically
measured by the energy consumed per
conversion and quantization step. The
dashed trend line represents a benchmark of the 1fJ/conversion-step. Circuit noise becomes more significant
with higher-resolution converters,
necessitating a different benchmark
proportional to the square of the signal-to-noise ratio, represented by the
solid line. Designs published from
1997 to 2019 are shown in circles.
ISSCC 2020 designs are shown in black
dots, which continue moving toward
the lower right of the figure.
Figure 4 shows the signal fidelity
versus the Nyquist sampling rate normalized to power consumption. At
low sampling rates, converters tend
to be limited by thermal noise, independent of the sample rate. Higher
speeds of operation present additional challenges in maintaining accuracy in an energy-efficient manner,
indicated by the roll-off versus frequency in the dashed line. The past
10 years have resulted in an improvement of more than 10 dB in powernormalized signal fidelity, i.e., a 10#
improvement in speed for the same
normalized signal fidelity. Of note at
this year's ISSCC is that two designs
are pushing toward thermal-noiselimited efficiency, using delta-sigma
and noise-shaped SAR architectures.
A pipelined SAR architecture delivers record-setting performance in
the speed-versus-efficiency corner of
the graph.
Figure 5 illustrates the ADC bandwidth as a function of the SNDR.
Sampling jitter and aperture errors
coupled with an increased noise bandwidth make achieving high resolution and bandwidth a particularly
difficult task. While a state-of-the-art
data converter showed an aperture
error of approximately 1ps rms 10
years ago, designs with aperture
errors below 100 fs rms have been
published in recent years. ISSCC 2020
further advances the state of the art
with an extremely high-performing,
time-interleaved pipeline architecture that surpasses the 100-fs rms
aperture line.

1.E+09
1.E+08
1.E+07
1.E+06
10

50 60 70 80
SNDR at fin,hf (dB)

100 110 120

FIGURE 5: The bandwidth versus the SNDR. psrms: picoseconds/root mean square.

IEEE SOLID-STATE CIRCUITS MAGAZINE

WINTER 2020

IEEE Solid-States Circuits Magazine - Winter 2020

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