IEEE Solid-States Circuits Magazine - Winter 2020 - 38

good idea to include a fast proportional
path (i.e., small delay, no decimation).
When optimizing the CDR architecture, it is important to budget
for CDR's self-generated jitter. The
budget can determine the choice
between LC versus ring VCO, and current mode logic versus CMOS clock
distribution, or may force a dedicated regulated supply for the clock
path. Power-supply-induced jitter may
sometimes be a large portion of the
self-generated jitter.
CDRs have limited locking range,
and, although gear-shifting the CDR
settings during initialization can
increase the range, it is often not
enough. Therefore, when architecting
the CDR, it is important early on to
determine the initial frequency-acquisition method (Note that frequency
acquisition was not covered in this
article.) Many systems allocate an initialization state, during which a clock
signal is sent over the data line by the
Tx and can be used by the Rx for the initial frequency acquisition. Other standards require the Rx to acquire a lock
without any special training sequence.
Examples of some CDRs with broad
capture range techniques can be found
in [24]-[26].
Clock recovery circuits often interact with the equalization circuits, as
the choice of sampling phase determines the sampled channel response
of the system. Therefore, it is important to simulate clock recovery with
data recovery.
Many of today's systems require
fast transitions between the powerdown state and the active state. In
such cases, fast wake-up CDR architectures are required. In digital CDR
architectures, frequency information
may be stored and recovered between
states; however, phase information
must still be acquired after every
state transition. Some examples of
fast wake up CDR architectures can be
found in [2].

Acknowledgments
I thank Dr. Valentin Abramzon, Dr.
Anup Jose, Prof. Sam Palermo, and
Prof. Ali Sheikholeslami for their

38

WINTER 2020

valuable feedback and help with preparing this article.

References

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IEEE SOLID-STATE CIRCUITS MAGAZINE

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About the Author
Amir A m i rk h a ny (a.amirkhany@
samsung.com) received his B.S. degree
from Sharif University of Technology,
Tehran, Iran, his M.S. degree from the
University of California, Los Angeles,
and his Ph.D. degree from Stanford
University, California, all in electrical
engineering. He is a senior director
of engineering at Samsung Electronics, in charge of the development of
future generations of high-speed interfaces for Samsung displays. Prior to
Samsung, he was a design manager at
Ramus Inc., where he led the development of proprietary high-speed
memory interfaces. He won the best
student paper award at the 2008 IEEE
Global Communications Conference,
has authored or coauthored over 25
IEEE conference and journal papers,
and has more than 40 issued U.S. patents. He is a Senior Member of the IEEE.
https://ocw.mit.edu http://literature.cdn.keysight.com/litweb/pdf/5989-0223EN.pdf http://literature.cdn.keysight.com/litweb/pdf/5989-0223EN.pdf http://literature.cdn.keysight.com/litweb/pdf/5989-0223EN.pdf
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