IEEE Solid-States Circuits Magazine - Winter 2021 - 10

0

Vout

M1

C1

-20

-40

Amplitude (dB)

VB +
-
Vin

-20

M4

X

Amplitude (dB)

M2

P

-60
-80
-100
-120

-40
-60
-80
-100

-140

(a)

0.5

1
1.5
Frequency (GHz)

2

2.5

(b)

2.3

2.35
2.4
2.45
Frequency (GHz)

2.5

(c)

FIGURE 6: (a) A sampler using ideal switches M2 and M4. (b) The output spectrum for fin = 570 MHz. (c) The output spectrum for fin = 2.47 GHz.

is aliased to fCK - 5fin = 2.15 GHz,
exhibiting a normalized level of
-110 dB. Next, we raise fin to 2.47 GHz
and note that its third harmonic appears at fCK - 3fin = 2.41GHz. Depicted in Figure 6(c), the output
spectrum yields HD 3 = - 64.4 dB, 1.3 dB
higher than the track-mode distortion found in the preceding. This can

CK
P M2
VB

X
M4

+
-

Vin

CK

Vout

M1

C1

FIGURE 7: The realization of M2 and M4.

-

CK
vin

M6

M4
CK
M3
M1

At this point, we wish to implement
M 2 and M 4 in Figure 6(a) by using
MOS devices. We recognize that M 4
must be an NMOS device because it
pulls X to the ground, whereas M 2
must be a PMOS device as it ties X
to a high potential (Figure 7). But we
must also decide to which node the
n-well of M 2 should be connected.
If attached to X, the n-well is drawn
toward the ground by M 4 when M 2
is off, thereby forward-biasing the
junctions between the n-well and the
source and the drain of M 2. To avoid
this issue, we tie the n-well to node P.

-20

vout
C1

Amplitude (dB)

VB

X

+

Sampler With MOS Switches

0

CK
P M2

be a
- ttributed to the channel charge
injected by M 1 onto C 1 in Figure 6(a);
even though VGS1 is constant, the
transistor's threshold is not, modulating the charge as Vin varies.

-40
-60
-80
-100
2.3

(a)

2.35
2.4
2.45
Frequency (GHz)
(b)

2.5

FIGURE 8: (a) The addition of switches to disengage VB in the hold mode. (b) The output
spectrum for fin = 2.47 GHz.

10	

W I N T E R 2 0 2 1	

IEEE SOLID-STATE CIRCUITS MAGAZINE	

The minimum widths of M 2 and
M 4 are dictated by the following constraints. We note that R on2 and the
total capacitance at X-primarily, the
gate source capacitance of M 2 -form
a low-pass filter, attenuating the input swing as it reaches X. Thus, R on2
must be chosen so that it provides a
bandwidth far beyond 2.5 GHz. This
is readily possible with a W 2 of a
few microns. We select W 2 = 2.5 nm.
Moreover, M 4 must pull X down at a
high slew rate so as to rapidly turn
off M 1. If it does not, the on-resistance of M 1 increases slowly, causing
distortion. We select W 4 = 2.5 nm for
now. For the clock driving these two
switches, we choose 10-ps rise and
fall times, as a representative in
28-nm technology.
Upon simulating the topology of Fig--
ure 7 with fin = 570 MHz and 2.47 GHz,
we obtain an HD 3 of -68 and -58 dB,
respectively. Why is the linearity degraded by such a large amount? The
reason is that M 2 fails to turn off for
part of the input swing: if Vin 2 0.5 V,
then VP 2 1.5 V, keeping M 2 on, even
if its gate is raised to 1 V. Consequently, M 4 cannot pull X to zero, and M 1
does not completely turn off.
To resolve this issue, we must remove the bootstrapping action in the
hold mode. That is, the battery must
be disconnected from the analog input. We thus add switches M 3 and M 6
[Figure 8(a)]. Now, when CK is high,
VB generates VP = VDD, allowing M 2 to
turn off. The gate of M 3 could not be
driven by the rail-to-rail clock b
- ecause
IEEE Solid-States Circuits Magazine - Winter 2021

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