IEEE Solid-States Circuits Magazine - Winter 2021 - 11

the on-resistance of M 3 would vary
considerably in the track mode. For
this reason, we bootstrap its gate to
Vin in a manner similar to M 1. The onresistance of M 3 should be comparable to that of M 2 and not limit the
bandwidth at node X. We tentatively
choose W 3 = 2.5μm and W 6 = 1 nm.
Simulations indicate an HD 3 of -84
and -60 dB for fin = 570 MHz and
fin = 2.47 GHz, respectively. The latter case is shown in Figure 8(b). The
circuit performs satisfactorily at this
stage of the design.
In the last step, we replace the
bootstrapping battery with a capacitor, as indicated in Figure 1(b). This
requires that M 5 be added so that
C B can be charged to VDD in the hold
mode. Several questions arise. First,
to which node should the gate of M 5
be connected? If driven as in Figure 9(a),
M 5 fails to turn off when CK is high
because VP = Vin + VDD can reach
1.75 V. We therefore surmise that the
gate of M 5 must be bootstrapped to
Vin as well [Figure 9(b)]. Second, to
which node should the n-well of M 5
be connected? For the same reason
mentioned for M 2, this n-well must
be tied to node P.
The third question relates to
the minimum acceptable value of
C B. Two effects play a role here.
When C B is switched to X, it experiences charge sharing with the
total parasitic capacitance at this
node, thereby providing a bootstrapping voltage that is less than

VDD. The parasitics at X include the
gate capacitances of M 1, M 3, and M 5
(the first two conducting and the
third remaining off) and the drain
capacitances of M 2, M 4, and M 5.
Thus, C B must be large enough to
minimize the voltage loss. For C B to
fully charge to VDD during the hold
mode, the series combination of
M 5, C B, and M 6 must exhibit a time
constant that is less than half of the
clock period. As an example, with
TCK /2 = 100 ps and C B = 0.25 pF, the
total on-resistance of M 5 and M 6
must remain lower than 400 X.
W e s e l e c t C B = 0.25 pF a n d
W 5 = 2.5 nm in Figure 9(b) and increase W 6 from 1 to 2.5 nm. The
simulation yields an HD 3 of -63 dB
at fin = 2.47 GHz. To assess the bootstrapping ability of C B, we plot its voltage as a function of time [Figure 9(c)].
We observe that C B charges to only
0.895 V (rather than to VDD = 0.95 V)
due to the long time constant. Moreover, the bootstrapping voltage is less
than 0.83 V due to charge sharing.
From the difference between 0.895
and 0.83 V, we estimate a parasitic capacitance of 20 fF at node X.
To improve the charge replenishment of C B, we must further widen
M 5 and M 6, and to remedy the charge
sharing, we must increase the value
of C B . Of course, an excessively wide
M 5 raises the parasitic at X and exacerbates the problem of charge sharing. Let us then choose C B = 500 fF,
W 5 = 5 nm, and W 6 = 5 nm. Simula-

tions still suggest an HD 3 of -63 dB
at fin = 2.47 GHz. We face diminishing returns, partially because the
large parasitic at X now creates a
long time constant with M 4, slowing
down the turn-off transition of M 1.
This is alleviated by increasing W 4
to 5 nm. The circuit now exhibits an
HD 3 of -65 dB at 2.47 GHz.

Device Stress Issues
The topology of Figure 9(b) applies
a drain source or gate source voltage well above 1 V to two of the
MOSFETs in the track mode. Called
device stress, this effect degrades
the transistors' performance over
time. We recognize that, when it
is off, M 4 experiences a peak drain
source voltage of Vin + VDD . 1.75 V.
Similarly, M 2 sees the same voltage
difference between its gate and its
source. To protect the former, we
place a cascode device in series with
it. As depicted in Figure 10(a), M 8
shields M 4, ensuring that VDS4 1 VDD;
M 8 itself sustains a maximum VDS of
1.75 V - (VDD - VTH4) . 1.05 V. The
series action of these two devices demands that they both be 10 nm wide.
The solution for reducing the
stress on M 2 in Figure 9(b) is more
complex. We note that the only possibility is to allow the gate voltage
of M 2 to change in unison with VX
and hence with Vin. That is, this
gate must be connected to Vin in
the track mode and to VDD in the
hold mode. Figure 10(b) -presents an

0.9
0.89

CK
VDD
M5

CK

P

P

VDD

Vin

+
-

CB

M5 +
VDD
CB CK
-
CK
M6
Vin

(a)

0.88

M2
X

Voltage (V)

VDD

M4

0.86
0.85
0.84

M3
M1
(b)

0.87

Vout
C1

0.83
1,800

2,000

2,200
Time (pS)

2,400

2,600

(c)
FIGURE 9: (a) A PMOS pull-up device driven by CK. (b) Bootstrapping the gate of M5 to Vin through VX . (c) The voltage across CB .

	

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