IEEE Solid-States Circuits Magazine - Winter 2021 - 40

spurious emission from UE A at the
frequency FC2.
The spectrum of a GSM Tx is presented in Figure 12. The most severe
case is when UEB is transmitting on
the uppermost channel of the Tx band
and UEB is receiving on the lowermost
channel of the Rx band. The frequency
offset in this case is only 20 MHz. The
standard specifies that the power (integrated over a 100-kHz bandwidth) at
a 20-MHz offset from the carrier frequency should be lower than −79 dBm

Desired

to ensure a UE does not desensitize
adjacent UEs. When the Tx power is
33 dBm, allowing for a 3-dB margin,
the total noise at a 20-MHz offset needs
to be at a −165 dBc/Hz level:
Tx NOISE @20 MHz = - 79 dBm
- log 10 " 100 kHz ,
- 33 dBm - 3 dB

= - 165 dBc .
Hz
The block diagram of a quadrature
Tx, presented in Figure 13, includes

PTx,High at FC2,UE_A

PRx,Low at FC,UE_B

Desired
BSB

BSA
Undesired

UEA

UEB

FIGURE 11: The near-far problem encountered in cellular transceivers.

PSD (dBm/100 kHz)
EGSM
Uplink Band

915

880

EGSM
Downlink Band

-79 dBm/
100 kHz

20 MHz

775

935

Noise-Corrupting Downlink Channel
FIGURE 12: The constraint on the maximum 2G Tx spurious emission to prevent adjacent Rx
desensitization; PSD: power spectral density; EGSM: extended GSM-900 band.

LPF
D/A

OSC

-156

-168
BBI
-168
LOI

Divide-By-4

-165
DA

LOQ
LPF
Q

D/A

BBQ

Noise Units dBc/Hz and at 20-MHz Offset

FIGURE 13: The noise budget for an in-phase (I)/quadrature (Q) architecture-based 2G Tx.
OSC: oscillator; D/A: digital-to-analog converter; DA: drive amplifier; Q: out of phase.

W I N T E R 2 0 2 1

annotations with the noise budget
for different sections of the chain.
Assuming equal noise contributions
from the signal and clock path, the
PN (20 MHz) of clock signal reaching
LOI and LOQ should be lower than
−168 dBc/Hz. LC oscillators are preferred over ring oscillators because
of their superior phase noise, at the
expense of a larger silicon footprint.
The clock-generation architecture includes an oscillator operating at 4×
the carrier frequency (4 × 922.5 MHz
= 3,690 MHz), followed by a divide by
4. Using a higher-frequency oscillator
offers two benefits: 1) the even-modulus divider generates quadrature
clocks required for the quadrature
mixer, and 2) a modulo-N noiseless
divider improves the phase noise by
a factor 20log10(N). A divide ratio of
4 would relax the oscillator phasenoise requirement to a challenging
but achievable −156 dBc/Hz at a 20-MHz
offset. It is also important to note
that 20 MHz would most likely lie
beyond the loop bandwidth of the
phase-locked loops (PLLs) and the
PLL will not suppress oscillator noise.
Oscillator design for GSM has become more challenging as the RFIC
transitions to nodes like 12 nm and
14 nm [23], [27]. The thin gate-oxide core devices, optimized for fast
switching, are susceptible to damage when used in circuits with voltage swings higher than the nominal
supply voltage (~1 to 1.1 V), such as
LC oscillators. However, phase noise
degrades in proportion to the square
of the oscillator voltage swing; when
there is a 2× reduction in oscillator
swing due to a shrinking supply voltage, the phase noise degrades by 12 dB
[12]. As a result, GSM continues to
employ an NMOS-only architecture to
maximize the signal and work with
higher supply-rails voltages available
in the chip.

IEEE SOLID-STATE CIRCUITS MAGAZINE

The 3G cellular standards employ
frequency-division duplexing (FDD)
to share the channel between the Tx
and Rx. In an FDD system, the Tx
and Rx operate simultaneously but at

IEEE Solid-States Circuits Magazine - Winter 2021

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