IEEE Solid-States Circuits Magazine - Winter 2021 - 42

is band specific. The input-referred
noise density of the Rx is

N Rx ^fRxh ; dBm E = - 174 + NF.(3)
Hz

Assuming the system allows for
0.5-dB SNR degradation due to the Tx
noise, the total Tx noise leaking at
the Rx can be estimated using
0.5=10log 61+10^NTx @Rx - N Rx @Rxh/10@.(4)
The noise is reflected to port n1 by
adding G ISO. Assuming the PA is
noiseless, the noise spec of the RFIC
can be estimated as

N RFIC ^fRxh @RFIC ; dBm E =
Hz

N Tx ^fRxh @Rx + G ISO - PA GAIN. (5)

Assuming GISO = 47 dB, PAGAIN = 25 dB,
and NF = 2.5 dB, the Tx noise at the
duplexer offset frequency should be
lower than −160 dBm/Hz.
In the early days, to satisfy the Rx
desensitization goals, a band-specific
Tx SAW filter at the duplexer offset frequency would be added in the signal

path. The cost and area implications
of adding the SAW filter were highlighted previously. To eliminate the Tx
SAW filter, the noise contributions of
the upconversion mixer and the clock
path need to be reduced. In [14], to reduce the mixer noise, a translational
loop was added across the mixer to
create a notch at the duplexer offset
frequency. A passive mixer with 25%
duty-cycle clock signals, displayed in
Figure 17, was described in [15]. The
key idea here is that 1) the transconductance stage converting voltage to
current is eliminated, 2) the techniquescaling friendly noise is proportional
to the mixer switch size (as the minimum feature size reduces the mixer
noise will reduce), and 3) applying a
25% duty cycle eliminates coupling
between the in-phase and quadrature
signal paths, which improves the gain
of the mixer to -0.9 dB, i.e., 3 dB higher
compared to the 50% counterpart.

Power Optimization
To this point, we have discussed
system-level specifications and how

Pn 2(f )
PRx-GIL

ANT

NTx at Rx-GISO at DUPL

FFRxRX

FTX
Tx

FFDUPL
DUPL
FIGURE 16: The Tx noise at the Rx frequency leaking into the Rx signal path due to finite
duplexer isolation.

+
BBQ

LOQ
+

LOI

BBQ

LOQ

VRF

LOQ

BBI

LOI

LOQ

BBI

LOI

FIGURE 17: A Tx passive mixer with a 25% duty cycle clock [15].

W I N T E R 2 0 2 1

IEEE SOLID-STATE CIRCUITS MAGAZINE

T/4

they impact the block design. Now,
we take a slight diversion to describe
techniques relevant for multimode operation. The brute-force approach for
multimode design would involve having a dedicated transceiver chain optimized for each standard. However,
this results in a suboptimal chip size.
The block diagram in Figure 15 includes
a reconfigurable PLL to support both
2G and 3G operation. Since bands allocated for 2G are contained within
the 3G bands, the dual-mode operation does not incur any penalty in the
tuning range. However, the critical
frequency offset at which phase noise
corrupts the system performance differs for the two standards. A 2G oscillator is optimized for phase noise at a
20-MHz offset (see the " Tx VCO Phase
Noise " section), whereas, for 3G B1,
the critical offset is 190 MHz (see the
" Upconverter Noise in the Rx Band "
section). The absolute noise power
governed by the standard's requirements varies for 2G versus 3G. A 2G
Tx (power class 3) delivers an output
power of 33 dBm, ~10dB higher than
a 3G Tx. Since the Tx oscillator phase
noise rides on the Tx signal, higher
signal power translates to a higher
oscillator noise contribution as well.
As discussed in the " Tx VCO Phase
Noise " section, stringent phase-noise
specification drives 2G oscillators to
employ an NMOS-only architecture at
a higher supply voltage to maximize
clock swing and minimize the phasenoise. This topology is power hungry
and not suited for 3G transmission.
The 3G-mode voice-mode (Tx operating at backed-off power levels) power
consumption is an important metric.
The Tx signal path can be architected
to scale the power drawn from the
battery as the output power reduces;
however, the clock path might not
scale proportionally. Therefore, for
3G, a good option is to trade off the
relaxed phase-noise requirement to
reduce power consumption.
An example of a reconfigurable oscillator that satisfies dueling requirements
of low phase noise and low power (not
simultaneously, though) is presented
in Figure 18. While transmitting 2G

IEEE Solid-States Circuits Magazine - Winter 2021

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