IEEE Solid-States Circuits Magazine - Winter 2021 - 47

will degrade the SNR if they fall inband. Every CA interference scenario
has to be analyzed when determining the Rx frequency plan. Consider
the example of B7 NCCB, which is illustrated in Figure 27. The UE is transmitting to the BS at 2,565 MHz and
receiving two component carriers at
2,625 [called the primary component
carrier (PCC)] and 2,685 MHz [called
the secondary component carrier or
(SCC)]. In the dual-PLL Rx architecture
described in Figure 28, the two PLLs
will contain an oscillator operating at
an N-times higher frequency, followed
by a modulo-N divider. The standard
approach would be to use N = 2, resulting in oscillator frequencies of 5,250
and 5,370 MHz. With this local oscillator (LO) generation plan, the mixing
product of the VCO_SCC and Tx falls
in band (5,250 − 2,565 = 2,685) with
the Rx_PCC, resulting in SNR degradation. Therefore, this architecture is
sensitive to any coupling path through
which the Tx signal could couple into
the Rx_PCC oscillator.
To avoid the aforementioned interference paths, in CA transceivers, judicious placement of the PLL
is required to minimize the on-chip
coupling paths. In addition, using
alternate divide ratios (other than 2)
can be considered.

Summary and Conclusion
This article covered various aspects
of a multimode cellular RFIC design
using examples. This is only the tip
of the iceberg. It is important to highlight that none of the circuit topologies discussed in this article can lay
claim to being a " globally " optimal solution. The interplay among systemcircuit codesign is what makes this an
exciting area for innovation.

Acknowledgments
I thank Prasad Gudem and Sang Won
Son for their valuable help in preparing this article.

References

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About the Author
Venumadhav Bhagavatula (bvenum@
gmail.com) received his B.E. degree in
electronics and communication from
the University of Delhi, New Delhi, India; his M.Tech. degree in electronic
design technology from the Indian Institute of Science, Bangalore; and his
Ph.D. degree in electrical engineering
from the University of Washington, Seattle, in 2005, 2007, and 2013, respectively. Since 2014, he has been with the
Advanced Circuit Design group at Samsung Semiconductors Inc., San Jose,
California, USA. His research interests
include radio-frequency/millimeterwave and low-power mixed signal circuits. He currently serves as a technical
program committee member for the
IEEE International Solid-State Circuits
Conference and an IEEE Solid-State Circuits Society Distinguished Lecturer.


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