IEEE Solid-States Circuits Magazine - Winter 2021 - 49

As the complexity of the modern system-on-chip
platform continues to grow, it is likely to require
numerous high-performance PLLs.
modes, which often necessitates redundant resistors and/or capacitors. Lastly,
since the control signal is mostly in an
analog domain, any interferences coupled to those analog components can
cause disturbances to the PLL's phase,
degrading the phase noise floor and/
or spurious tones.
Driven by the aforementioned limitations, there has been a recent push
in the frequency synthesizer design
community toward a more digitalintensive approach, namely digital
PLL or all-digital PLL. The key idea is
to replace most of the analog computation with digital circuits, as demonstrated in Figure 1(b). Since the PLL
loop filter is entirely implemented in
the digital domain, the area consumption is substantially reduced, and the

filter response is highly reconfigurable and insensitive to any process
variability. The overall architecture
becomes much more scalable with
technology and allows the use of digital logic design flow to further reduce
design time.
The evolution of digital PLL can be
roughly divided into three waves. The
first wave focuses mainly on reducing
the area consumption thanks to the
digital implementation of the digital
loop filter, where Moore's law has been
the key enabler. However, the digital
PLL architecture inevitably incurs quantization noise to process the phase
information in the digital domain.
Therefore, in the second wave, designers focused mainly on minimizing the
overheads of the digital PLL to reduce

× Headroom × Leakage
× External Noise
× Matching × Area Consuming Coupling → Spurs
× Noise
Fref
PFD

CP
Analog
Digital
/N
(a)

Fref

No Leakage
Noiseless
Small Area
Flexible (Type I, II, III)
Digital
PFD

Digital
Filter

× External Noise
Coupling → Spurs

DAC

hase-locked loop
(PLL)-based frequen-
cy synthesizers are
-
pervasively utilized
in almost every electronic system for generating welldefined clock frequencies of interest.
For instance, in a modern wireless
transceiver, a radio-frequency (RF)
synthesizer is typically used as a local
oscillator to upconvert/downconvert
the desired signal to and from the
proper communication bands. A similar utilization of RF PLL can be seen in
a wireline transceiver, which modulates and demodulates the data symbol at a precise frequency and phase.
In addition to RF applications, PLL is
also commonly used in baseband and
digital circuitry, such as generating a
sampling clock for switched-capacitor
circuits and clocking the sequential
logic of the digital circuitry. As the
complexity of the modern system-onchip (SoC) platform continues to grow,
it is likely to require numerous highperformance PLLs. Moreover, interference coupling through the same
silicon substrate is exacerbated. As a
result, the low implementation (area
and power) cost, high reconfigurability, resilience over interferences, and
reduced design time of a PLL have
become increasingly important in light
of this new trend.
Conventionally, the frequency synthesizer is implemented using an analog approach, commonly referred as
the charge pump PLL or analog PLL,
as depicted in Figure 1(a). While this
topology has been widely adopted
and proven in both the literature and
commercial products, it presents a
general challenge for technology scaling. The analog loop filter is typically
composed of bulky passive components whose values are mainly determined by the desirable PLL bandwidth
and cannot be arbitrarily reduced.
Additionally, the leaky device and
lower supply voltage in the scaled
technology impose headroom and a
matching issue to the charge pump
circuits. Another drawback of the analog
approach is the lack of easy programmability to support different operation

Analog
TDC
× DAC Noise
Digital
× TDC Noise
× TDC Gain

Calibration
(b)
FIGURE 1: A simplified block diagram of (a) an analog charge pump (CP) PLL and (b) a digital
PLL. DAC: digital-to-analog converter; TDC: time-to-digital converter; PFD: phase-frequency
detector.

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