IEEE Solid-States Circuits Magazine - Winter 2021 - 51

It shows the same low-pass transfer
function as the closed-loop PLL inputto-output response. Therefore, the TDC
quantization noise will degrade the inband phase noise.
Similar to an analog-to-digital converter (ADC), a TDC can either be multibit
or single-bit, as illustrated in Figure 3.
While the implementation of a singlebit TDC is much simpler than the N-bit
case, its quantization noise increases
proportionally with the input value,
and the gain is input-signal dependent. This imposes the uncertainties
of the PLL loop dynamics. For the N-bit
TDC, the single-side-banded, in-band
phase noise spectral density can be
approximated as (5), assuming the
quantization noise is white and uniformly distributed:

L SSB ^dBc/Hz h = 10 log c
∆{ =

∆ {2 2
m,
12 Fref

t LSB
$ 2r,
Tdco

In general, the frequency quantization noise
impact is manageable via proper design and is
negligible in the overall PLL phase noise.
the desired ratio of (N + 1/m), as illustrated in Figure 4(a). As a result, there
is associated quantization error with
this dithering of the feedback divider
ratio, degrading the overall phase noise.
To mitigate this issue, one can rely
on either the loop filter to reduce the
noise or on a more complex noise cancellation loop [1], [2].
Another fractional-N digital PLL
architecture injects the integral of frequency multiplication ratio right after
the TDC [3], [4]. As demonstrated in

Ideal PD

(5)

Multibit TDC

Derr

where t LSB is the least significant bit
(LSB) resolution of the TDC and Tdco is
the DCO period. Note that the quantization noise in some fractional-N digital
PLL architecture can present a repetitive pattern and hence generate fractional spurious tones, as discussed in
the next section.

the embodiment of Figure 4(b), there
is no additional noise associated with
the fractional frequency generation
in the case of an ideal TDC. In reality,
the TDC has a finite resolution, and
its quantization noise introduces a
repetitive phase error to the PLL loop
since the phase difference between
the reference and feedback signals
constantly increases at the rate determined by the fractional divider ratio.
Since the input of the TDC shows a
deterministic ramp pattern, the TDC

Single-Bit TDC

Derr

∆Φin

Qerr

∆Φin

Qerr

Fractional-N Operation
∆Φin

∆Φin

Fref

Digital
Filter
÷N

(÷ N +1/m)
1/m
Divider
N +1
N
N -1
1/m

DAC

Digital
Filter

TDC

Fref

DAC

FIGURE 3: A transfer function and quantization noise profile of multibit versus a single-bit
TDC compared with an ideal analog phase detector (PD).

TDC

In some application scenarios, the frequency multiplication ratio of the PLL
is not an integer number, typically
referred as fractional-N operation. That
way, one can increase the input reference clock's frequency or fine-tune the
output frequency at a finer step, which
may be desirable for some systems.
For the fractional-N operation, there
are two popular approaches to generate the fractional frequency multiplication ratio, as depicted in Figure 4. One
approach is to apply a multimodulus fractional divider that utilizes a
delta-sigma modulator in the feedback
divider path. The idea is to divide the
DCO frequency by a few possible integer division ratios, i.e., N - 1, N, and
N + 1, and so on, for different reference clock cycles, such that the average division ratio over time equates

Σ
(b)

∆ΣM
(a)

FIGURE 4: Two popular fractional-N digital PLL architectures with (a) a multimodulus divider
and (b) a frequency accumulator.

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