IEEE Solid-States Circuits Magazine - Winter 2021 - 56

Thanks to the inherited DSP capability and
technology scaling, there are plenty of new
opportunities for this mostly digital PLL
topology to excel beyond traditional analog
PLL architecture.
As indicated in Figure 8(b), a predetermined dither signal is applied to the
input reference buffer, allowing a least
mean square (LMS) algorithm to learn
the transfer function of the two coupling paths. It then enables the pulling
compensation signals to be injected
at the input and output of the digital
loop filter and mitigates the pulling
effect. In short, this architecture facilitates a more robust frequency synthesizer and can be useful for future
SoC integration.

Conclusion
In this review article, we have examined the design basics and trends
of digital PLL architectures. Thanks
to the inherited DSP capability and
technology scaling, there are plenty
of new opportunities for this mostly
digital PLL topology to excel beyond
traditional analog PLL architecture. It
is very likely that we will continue to
witness more exciting digital PLL techniques in the years to come.

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About the Author
Mike Shuo-Wei Chen (swchen@usc
.edu) received his B.S. degree from
National Taiwan University, Taipei, in
1998 and his M.S. and Ph.D. degrees
from the University of California,
Berkeley, in 2002 and 2006, all in electrical engineering. He is an associate
professor in the ECE Department at
the University of Southern California
(USC), Los Angeles, California USA. As a
graduate student researcher, he proposed and demonstrated the asynchronous successive approximation register
analog-to-digital converter architecture,
which has been adopted today for lowpower, high-speed analog-to-digital
conversion products in industry. At
USC, he leads an analog mixed-signal
circuit group, focusing on data converters, radio-frequency synthesizers,
transceiver, and nonuniformly sampled
circuits and systems.
IEEE Solid-States Circuits Magazine - Winter 2021

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