IEEE Solid-States Circuits Magazine - Winter 2021 - 8

10 log of the result, and equate it
to -1 dB. With T = 1mV and T = 75c
C = 348 K, we obtain C 1 = 445 fF,
which we round up to 0.5 pF.
Third, the low-pass filter formed
by M 1 and C 1 in Figure 1(b) must
negligibly attenuate the input signal
in the track mode. The output amplitude is equal to A/ 1 + R 2on1 C 12 ~ 2in ,
where R on1 denotes the on-resistance
of M 1. We aim for an attenuation less
than 0.5 dB at the Nyquist rate, arriving at R on = 44.5 X. We should
select M 1 so that it is wide enough
to ensure such a low resistance with
VGS1 . VDD = 0.95 V. This constraint
yields W 1 . 10 nm if L 1 = 28 nm.

son not to do so. In this article, all
channel lengths are equal to 28 nm.

Simulation Issues
In the design of sampling circuits,
the clock and the input frequencies
must be carefully chosen. If fCK is an
integer multiple of fin, then the circuit samples only certain points on
the input waveform [Figure 2(a)], failing to reveal its true performance.
Even if we select fCK /fin = P/Q , where
P and Q are integers, we still have
QTin = PTCK, where Tin = 1/fin. This
means that every Q cycles of the input exactly coincide with P cycles of
the clock; thus, only Q values of the
input are periodically sampled. For
this reason, we should select fCK and
fin such that the samples gradually
slide along the input sinusoid and
eventually assume all (or most) of
the input values [Figure 2(b)]. This
is accomplished if fCK /fin is an irrational number. For simulations, we
simply guarantee that P/Q yields a
long periodicity. For example, with
fCK /fin = 5 GHz /570 MHz = 500/57,
the sampled points repeat themselves after every 500 clock cycles;
i.e., 500 distinct points of the input
voltage are collected.
Another issue relates to how we
process the output time-domain
waveform in Figure 1(b) to go to the
frequency domain. Since the ADC following the sampler senses only the
held values on C 1, the time points
taken by the fast Fourier transform
(FFT) must be confined to the hold
mode [Figure 3(a)]. That the ADC digitizes only the held values also sug-

Design Procedure
To understand the effect of device
nonidealities, we follow an incremental design procedure. Specifically, we proceed in five steps: 1) we
keep the battery in Figure 1(a) and
examine the distortion in only the
track mode; 2) we allow the circuit to
act as a sample-and-hold stage but,
except for M 1 in Figure 1(b), use ideal
switches; 3) we change M 2 and M 4 to
MOS devices; 4) we change the remaining switches to MOSFETs; and 5)
we replace the battery with a capacitor. In each case, we apply the fullscale input amplitude and measure
the harmonic content of the differential output at a moderate input frequency and at the Nyquist rate. The
incremental approach also permits
us to optimize the design in every
step. We prefer to select minimum
widths and lengths for the transistors unless there is a compelling rea-

Vin
t
(a)
Vin
t
(b)
FIGURE 2: Sampling the input with (a) an integer fCK/fin ratio and (b) an irrational fCK/fin ratio.

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IEEE SOLID-STATE CIRCUITS MAGAZINE	

gests that the sampler-ADC cascade
equivalently multiplies the analog
input by a train of impulses in the
time domain [Figure 3(b)] and hence
convolves the input spectrum with
a train of impulses in the frequency domain [Figure 3(c)]. We call the
range between - fCK /2 and + fCK /2
the first Nyquist zone and generally
confine our inspection of unwanted
components to this region.
If the FFT senses only the values at t 1, t 2, and so on, the resulting
spectrum is given by the convolution of the input spectrum and a
train of impulses. This point proves
useful in understanding the FFT results. For example, if the sampler
introduces third-order distortion at
3fin and this component lies above
fCK /2, then it is aliased to the first
Nyquist zone. Depicted in Figure 3(d),
this phenomenon causes the third
harmonic to land at fCK - 3fin.

Track-Mode Distortion
We begin by simulating two instances of Figure 1(a) with differential inputs and fin = 570 MHz. As
mentioned, W 1 = 10 nm for now.
We surmise that this test yields a
lower bound for the distortion because higher input frequencies and
the sample-and-hold action tend
to introduce greater nonlinearity.
Figure 4 plots the FFT of the differential output. As expected, even
harmonics are absent. The third and
fifth harmonics are 79 and 97 dB below the fundamental, respectively.
We denote the relative level of the
former by HD 3 and that of the latter by HD 5. Next, we increase fin to
2.47 GHz and repeat the simulation.
Figure 5(a) shows the time-domain
outputs, revealing a peak-to-peak
single-ended swing of 483 mV, which
satisfies our attenuation constraint of
0.5 dB. The output spectrum is plotted in Figure 5(b), exhibiting a third
harmonic at -56 dB. This high level of
distortion occurs because R on1 varies significantly due to the body effect. As explained in [4], the output
phase then varies considerably with
the input voltage. We must therefore
reduce R on1. Changing W 1 from 10 to
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