IEEE Solid-States Circuits Magazine - Winter 2022 - 10

first latch " recover " from the previous,
large overdrive and still respond
correctly. Illustrated in Figure 6 is the
overdrive recovery, where Vsum
+
Vsum
-
and
denote the summer outputs. If
the first latch begins to sense Vsum
+
and Vsum
-
at tt ,1= then the latch output
voltages in Figure 5 must cross
before the circuit enters the regeneration
mode. That is, we must have
tt /.T 2CK21
nario with V 70mV, arriving at AW / L [11]. With A 4mVm,
we have VTH ,12 .10mV. The threshold
mismatch between M3 and M4
- 1
We simulate the FF in such a sce0
=
the results plotted in Figure 7(a). The
latch output voltages barely cross
before regeneration begins. Thus, in
the presence of offsets due to M1
or M3
-M2
-M ,4
the circuit produces an
incorrect output. Figure 7(b) depicts
the outputs for V 100mV,
0 =
revealing
more robust sampling. Thus,
in addition to overcoming various
offsets and noise contributions at
the summing junction, the swing
must include at least another 100 mV
Vsum
+
V0
Vsum
-
t
VX
VY
t1
t2
t
FIGURE 6: The latch overdrive recovery.
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
DFE Design
We implement the DFE architecture
of Figure 2 as shown in Figure 9.
The summer senses the CTLE output
voltage, converts it to current
by means of M1
and M ,2
result to the output of M3
select W 10 mn=
adds the
and M ,4
and allows the sum to flow through
the load resistors. For M1
and M ,2
we
so as to give their
Figure 5 as T VTH ,12
VTH
T
has the same standard deviation, but
it is divided by
gR /ggmD mm12
-
,, ,
12
34
[6], which is about 2 in our design.
The 4v offset of L1
is, therefore,
around 45 mV.
The input-referred noise of the FF
can be computed using the method de -
scribed in [10] and is about ..
15mVrms
To this, we must add the CTLE and
summer noise. The simulated noise
spectrum shown in Figure 8 yields an
rms value of 2.6 mV integrated up to
100 GHz. It follows that V
nr, ms . mV
3
in (3), suggesting that the differential
eye height,
2 V ,T must exceed 132 mV.
VTH
.
$n
for proper FF behavior. Interestingly,
this value is greater than that
predicted by (2), implying that the
summing junction swing
is dictated by the FF overdrive
recovery rather than
noise and offset.
The FF offset is also
of interest. We write the
threshold mismatch
between M1
and M2
in
=
tail current source a reasonable voltage
headroom. The first tap is scaled down
by a factor of four according to our
impulse response study.
We also add 5-fF capaciSome
iteration in
the DFE tap values
may be necessary
if the greatest
eye opening
is desired.
tors at A and B as an estimate
of layout parasitics.
A number of points
should be borne in mind
regarding DFE simulations.
First, a proper phase
relationship must be established
between the summer output
and FF clocks. As our initial try, we
place the crossing points of VA
VB near those of CK and CK such
that, when CK goes high, L1
-
senses
VV .AB Second, the feedback provided
by M3 and M4
must be negative.
Third, we monitor the eye at
the summing junction, but we must
also ensure that the FF output indeed
matches the original data applied to
the channel. That is, an open eye does
not necessarily imply correct operation.
Fourth, the simulation must
run long enough (about 20 ns in our
example) so that the channel " settles, "
and the summer output represents
the steady-state behavior. We then
construct the eye diagram from the
last few nanoseconds.
Figure 10 plots the differential eye
diagrams at the CTLE and DFE summer
outputs. The DFE increases the
vertical opening by about 250 mV.
Next, we apply resistive and
capacitive degeneration to the summer
input stage (Figure 11). Providing
some linear equalization, this
method leads to the eye shown in
and
Din
+
Din
-
0.5
0.6
0.7
0.8
0.9
VX
VY
0.4
0.5
0.6
0.7
0.8
0.9
4.8 4.85 4.9 4.95 5
Time (ns)
(a)
FIGURE 7: The (a) input and output waveforms of a CML latch in an overdrive recovery test with V0
of V0
= 100 mV.
10 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
4.8 4.85 4.9 4.95 5
Time (ns)
VX
VY
4.8 4.85 4.9 4.95 5
Time (ns)
(b)
= 70 mV and (b) latch output for the case
Voltage (V)
Voltage (V)
Voltage (V)

IEEE Solid-States Circuits Magazine - Winter 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2022