IEEE Solid-States Circuits Magazine - Winter 2022 - 111

measures and restrictions will remain
uncertain for the upcoming months
across Europe and worldwide.
In transition toward a future
postpandemic event again, DATE
2022 will host a two-day live event
in presence in the city of Antwerp
(just north of Brussels in Belgium)
on 14-15 March 2022 to bring the
community together again, followed
by other activities carried out entirely
online on 16-23 March 2022. This
setup combines an in-presence experience
with opportunities for online
activities, fostering networking and
social interactions around an interesting
program of selected talks
and panels on emerging topics to
complement the traditional DATE
high-quality scientific, technical, and
educational activities.
Ph.D. Forum, Multi-Partner Projects,
University Fair, and Young People
Program submissions are due
on 15 November 2021. All deadlines
are strict, and no extensions will be
given. Please visit https://www.date
-conference.com/ to download the
call for papers for descriptions and
submission instructions.
Call for Participation: CEDA
Virtual Distinguished Lecturer
Webinar Series
The Virtual Distinguished Lecturer Program
(https://ieee-ceda.org/virtual-dlp)
allows us to continue to serve CEDA
participants and the EDA community
by giving them the opportunity
to hear from our respected distinguished
lecturers (https://ieee-ceda.org/
distinguished-lecturers-program). In
2021, the CEDA Virtual Distinguished
Lecturer Program has hosted six online
webinars with nearly 600 attendees
joining us from 42 countries around
the world, including those in Africa, the
Americas, Europe, and Asia. This virtual
format provides members of the EDA
community greater access to talks from
industry experts.
The last virtual distinguished
lecture webinar of the year features
Dr. Yier Jin of the University of Florida.
His presentation, " Hardware
Supported Cybersecurity for IoT, "
will be hosted on 18 November at
11 a.m.-12 p.m. Eastern Time (ET).
Registration is free but required
via Zoom (https://us06web.zoom
.us/webinar/register/8616177211964/
W N _ t TA 1M H l I QE Wo m _
bg9kAaXA).
In this talk, Dr. Jin will
first introduce the emerging
security and privacy challenges
in the IoT domain.
He will then focus on bottom-up
solutions for IoT
protection and present
a recent research effort
in microarchitecturesupported
IoT runtime
attack detection and
device attestation.
The developed methods will lead to
a design-for-security flow toward
trusted IoT and their applications.
Visit https://ieee-ceda.org/virtual
-dlp for a full listing of upcoming
webinars.
CAD for Assurance Panel: Security
Assessment and Verification for
Microelectronics-A New Future
or More of the Same?
IEEE CEDA's Hardware Security and
Trust Technical Committee (https://
ieee-ceda.org/technical-committee/
hardware-security-and-trust-technical
-committee) developed the " CAD for
Assurance " website (https://cadfor
assurance.org/) and tools for faculty,
students, postdoctoral researchers,
and practitioners in the hardware
security community to disseminate
their work. This initiative also includes
a series of monthly virtual webinars.
The next panel presentation, " Security
Assessment and Verification for
Microelectronics-A New Future or
More of the Same? " by Kevin Bush
(MIT Lincoln Lab), Sharad Malik
(Princeton), Keith Rebello (DARPA),
Robert B. Jones (Intel), and Jamin
McCue (Air Force Research Laboratory)
is on 8 October at 11 a.m.-
12:20 p.m. ET.
Registration is required (https://
zoom.us/webinar/register/84161393
80017/WN_C327OvykTgGuHHB3RcjBHg).
For more information on this webinar
series and to register, visit https://ieee
-ceda.org/cad-assurance.
He will then focus
on bottom-up
solutions for IoT
protection and
present a recent
research effort in
microarchitecturesupported
IoT
runtime attack
detection and
device attestation.
Call for Participation: Complete the
IEEE ESL and IEEE D&T Surveys
IEEE Embedded Systems Letters (ESL)
(https://ieee-ceda.org/publication/
ieee-embedded-systems
- l e t t e r s) and IEEE
Design & Test (D&T)
(https://ieee-ceda.org/
publication/ieee-design
test) want to hear from
you! Please complete the
feedback surveys for ESL
(https://www.surveymon
key.com/r/RZVY7KJ) and
D&T (https://www.survey
monkey.com/r/TKTGBZ6) by
visiting the links provided
in the text box. Your feedback
is important to the future success
of these journals. If you have
any questions regarding the surveys,
please contact us at admin@
ieee-ceda.com.
Call for Papers: IEEE Design & Test-
Special Issue on Design and Test of
Multichip Packages
From auspicious beginnings more
than 10 years ago, the promise of
3DICs has begun to turn the corner
to more popular usage. This D&T
special issue on multichip packages
focuses exclusively on design and
design for test for 3D, chiplet-based,
and stacked ICs, based on throughsilicon
vias, microbumps, and/or
interposers. While these stacked ICs
offer many attractive advantages with
respect to heterogeneous integration,
small form factor, high bandwidth
and performance, and low power dissipation,
there are many open issues
with respect to designing and testing
such products.
This special issue seeks original
manuscripts that will cover innovative
research and practical applications for
the testability and design challenges
on both pure 3DIC implementations
as well as other multichip packaging
implementations, including chiplets
and active and passive interposers.
The deadline to submit manuscripts
has been extended to 15 October 2021.
For a full list of topics, important dates,
and guest editors, visit https://ieee
-ceda.org/ieee-designtest.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
111
IEEE Solid-States Circuits Magazine - Winter 2022

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