IEEE Solid-States Circuits Magazine - Winter 2022 - 12

0.1
0.2
0.3
0.4
0.5
A proper phase
relationship must
be established
between the
summer output
and FF clocks.
-0.5
-0.4
-0.3
-0.2
-0.1
05 10 15 20 25 30 35
Time (ps)
FIGURE 12: The DFE summer eye diagram in the presence of degeneration.
VDD
RD
RD
FF1
FF2
FF3
References
[1] B. Razavi, " The design of an equalizer -
Part one, " IEEE Solid State Circuits Mag.,
vol. 13, no. 4, pp. 7-160, Fall 2021, doi:
10.1109/MSSC.2021.3111426.
[2] J. Im et al., " A 40-to-56 Gb/s PAM-4 receiver
with ten-tap direct decision-feedback
equalization in 16-nm FinFET, " IEEE J. Solid-State
Circuits, vol. 52, no. 12, pp. 3486-
3502, Dec. 2017, doi: 10.1109/JSSC.2017.
2749432.
[3] T. Shibasaki et al., " A 56-Gb/s receiver
front-end with a CTLE and 1-tap DFE in
20-nm CMOS, " in Proc. VLSI Circuits Symp.
Dig., Jun. 2014, pp. 1-2, doi: 10.1109/VLSIC.2014.6858400.
[4]
A. Roshan-Zamir et al., " A 56-Gb/s PAM4
receiver with low-overhead techniques
for threshold and edge-based DFE FIRand
IIR-tap adaptation in 65-nm CMOS, "
IEEE J. Solid-State Circuits, vol. 54, no.
3, pp. 672-684, Mar. 2019, doi: 10.1109/
JSSC.2018.2881278.
ISS1
250 µA
FIGURE 13: The addition of the third tap to the DFE.
ISS4
60 µA
[5] A. Cevrero et al., " A 100Gb/s 1.1pJ/b
PAM-4 RX with dual-mode 1-tap PAM4
/ 3-tap NRZ speculative DFE in 14nm
CMOS FinFET, " in Proc. IEEE Int. SolidState
Circuits Conf. (ISSCC), Feb. 2019,
pp. 112-113, doi: 10.1109/ISSCC.2019.
8662495.
[6] S. Ibrahim and B. Razavi, " Low-power CMOS
equalizer design for 20-Gb/s systems, "
IEEE J. Solid-State Circuits, vol. 46, no. 6,
pp. 1321-1336, Jun. 2011, doi: 10.1109/
JSSC.2011.2134450.
[7] B. Razavi, " The decision-feedback equalizer
[A
Circuit
0.1
0.2
0.3
0.4
0.5
-0.5
-0.4
-0.3
-0.2
-0.1
05 10 15 20 25 30 35
Time (ps)
FIGURE 14: The DFE summer eye with the third tap added.
The subsequent results remain
unchanged. Richard Schreier has
pointed out that the T-coil design
equations can also be derived by
decomposing N(s)
12 WINTER 2022
all-pass transfer function must
contain poles that mirror or cancel
its zeros.
In [13], the gates of Mc
and Md
into two quadratics
and using the fact that an
and Mb
, respectively.
in
Figure 9 should be tied to the drains
of Ma
IEEE SOLID-STATE CIRCUITS MAGAZINE
Solid-State Circuits Mag., vol. 9, no. 4, pp.
13-16, Fall 2017, doi: 10.1109/MSSC.2017.
2745939.
[8] P. Peng, J. Li, L. Chen, and J. Lee, " A 56Gb/s
PAM-4/NRZ transceiver in 40nm CMOS, "
in Proc. IEEE Int. Solid-State Circuits Conf.
(ISSCC), Feb. 2017, pp. 110-111, doi:
10.1109/ISSCC.2017.7870285.
[9] J. Lee and B. Razavi, " A 40-Gb/s clock and
data recovery circuit in 0.18um CMOS
technology, " IEEE J. Solid-State Circuits,
vol. 38, pp. 2181-2190, Dec. 2003, doi:
10.1109/JSSC.2003.818566.
[10] B. Razavi, " The design of a comparator
[The Analog Mind], " IEEE Solid-State Circuits
Mag., vol. 12, no. 4, pp. 8-14, Fall
2020, doi: 10.1109/MSSC.2020.3021865.
[11] M. J. M. Pelgrom, A. C. J. Duinmaijer, and
A. P. G. Welbers, " Matching properties of
MOS transistors, " IEEE J. Solid-State Circuits,
vol. 24, no. 5, pp. 1433-1440, Oct.
1989, doi: 10.1109/JSSC.1989.572629.
[12] B. Razavi, " The design of broadband I/O
circuits [The Analog Mind], " IEEE SolidState
Circuits Mag., vol. 13, no. 2, pp. 6-12,
Spring 2021, doi: 10.1109/MSSC.2021.
3072299.
[13] B. Razavi, " The design of a low-voltage
bandgap reference [The Analog Mind], "
IEEE Solid-State Circuits Mag., vol. 13, no.
3, pp. 6-13, Summer 2021, doi: 10.1109/
MSSC.2021.3088963.
for All Seasons], " IEEE
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IEEE Solid-States Circuits Magazine - Winter 2022

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