IEEE Solid-States Circuits Magazine - Winter 2022 - 13

CIRCUIT INTUITIONS
Ali Sheikholeslami
A Circuit to Remember
W
Welcome to the 31st article in the
" Circuit Intuitions " column series. As
the title suggests, each installment
provides insights and intuitions into
circuit design and analysis. These
articles are aimed at undergraduate
students but may serve the interests of
other readers, as well. If you read this
article, I would appreciate your comments
and feedback, as well as your
requests and suggestions for future
articles in this series. Please email me
your comments at ali@ece.utoronto.ca.
Two of the most elegant circuits
in the world of electronics belong to
dynamic random-access memories
(DRAMs). These circuits have been
around since the early days of the
DRAM and they continue to serve
us to this day. These are the basic
one-transistor-one-capacitor (1T1C)
memory cell, and its simple sense
amplifier (SA). In this article, we introduce
these circuits and review some
of their interesting characteristics.
The most basic element in electronics
that has storage capability
is a capacitor [1]-[3]. We can simply
store a digital 1 or 0 on a capacitor
by charging it to up to a full power
supply voltage ()Vdd
or by discharging
it to 0V, respectively. Depending
on the voltage difference between
these two levels (Vdd
in our example),
we have certain immunity
against leakage, noise, and interference
that may add to (or subtract
from) our stored voltage levels. If
,
V 1Vdd
=
any stored level higher than
05 . V can be interpreted as digital
Digital Object Identifier 10.1109/MSSC.2021.3127066
Date of current version: 24 January 2022
1 simply because it is closer to 1V
than to
0 .V Similarly, any voltage
level less than .05V can be interpreted
as a digital 0.
This simple storage mechanism
becomes more complicated when we
need to store thousands or millions
of bits side by side on an integrated
circuit. The first question that comes
to mind is how to access an individual
capacitor in a large array without
interfering with the others. A wellknown
technique to accomplish this
is to add a switch, called access transistor,
in
series with the capacitor
as shown in Figure 1. This minimal
configuration that consists of a single
transistor and a single capacitor
allows us to access certain capacitors
in an array simply by turning on their
corresponding transistors while turning
off the transistors of all other cells.
The 1T1C cell, as shown in Figure 1, is
probably the most used circuit in the
world of electronics. In fact, a typical
1-Gb DRAM that you find in most
cell phones and laptops today has
about one billion of these cells. Interestingly,
at the time of this writing,
the price for 1 billion of these cells is
around US$1.
Let us define some basic terms
related to 1T1C cell before proceeding.
We refer to the top plate of the
capacitor, the one connected to the
transistor, as the storage node of
the cell (denoted by S in Figure 1),
and to the bottom plate simply as
the capacitor plate. Also, the gate of
the access transistor is usually connected
to the gate of other cells in
the same row forming a wordline
(WL). Similarly, one terminal of the
access transistor is connected to
bitline (BL).
Let us now build a small 44#
array of memory cells as shown in
Figure 2 to review its properties
and requirements. A row of four
cells can be accessed simultaneously
by raising its corresponding
WL. For example, raising WL1 to Vdd
while keeping all other WLs at 0V
allows us to connect the capacitors
on that row to their corresponding
BLs (BL0 to BL3). The four independent
BLs will allow us to either
simultaneously read the stored data
from the cells connected to WL1 in
a read operation or simultaneously
write into them in a write operation.
We note that WLs and BLs are
usually made of metal strips to
have low resistivity; but they are
largely capacitive due to the cumulative
parasitic capacitances of all
of the cells connected to them. Let
us denote by CBL
tance of a BL and by CWL
the total capacithe
total
capacitance of a WL. Typically, a
WL may be connected to 1,024 cells
(1 kb), and a BL may be connected to
128-256 cells. A storage capacitor is
around fF30 and the BL capacitance
WL
S
CS
BL
FIGURE 1: A 1T1C memory cell.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
13
IEEE Solid-States Circuits Magazine - Winter 2022

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