IEEE Solid-States Circuits Magazine - Winter 2022 - 15

as references. Similarly, by selecting
WL1, BL0 and BL1 access the cells
while BL0 and BL1 serve as references.
In the schematic of Figure 3,
it appears that removing one-half of
the cells from each WL (as shown)
may result in not utilizing half of
the silicon area. But in the actual
layout, one cell will occupy the area
allocated to two BLs, hence no area
is wasted.
We now describe the read operaPRE
Time
WL1
Time
BL0
BL0
Time
SAN
SAP
tion
of this architecture using a
transistor-level schematic of a single
column consisting of
two BLs
(BL0 and BL )0 and two WLs (WL0
and WL1) as shown in Figure 4.
Every read operation begins by precharging
all of the BLs to (/ )V12 dd
using the two transistors at
the
top of the column. A third transistor
connects the two BLs to further
equalize their charges. In the timing
diagram of Figure 5, this corresponds
to the time interval between
tpre
and t .WL Next, we raise a WL
(WL1 in this example) to begin the
charge sharing between the storage
node and
.
BL0 This charge sharing
causes the voltage on BL0 to
increase slightly (assuming the cell
FIGURE 5: Timing diagram of a read operation for the circuit of Figure 4. This timing assumes
the data stored in the cell at the intersection of WL1 and BL0 is a 1.
is storing a 1) while BL0 remains
unchanged at its precharged level
of (/ ).V12 dd
Note that during this
period the SA, which consists of
two back-to-back inverters, remains
inactive and disconnected from the
supply and ground. At
t ,SA we activate
the SAN and SAP signals, and
the SA begins to amplify and regenerate
the initial voltage difference
between the two BLs toward full
V .dd
During this regeneration proVdd/2
PRE
WL0
BL0
BL0
cess
and for a short time after, we
keep the WL activated, allowing the
SA to write back to the cell, restoring
the original stored data. This is
exactly how the SA plays the double
role of read and restore operation,
one after the other.
To ensure the data stored is not
WL1
SAP
SAN
FIGURE 4: A simplified transistor-level
schematic of a column of a memory array.
This corresponds to the leftmost column in
Figure 3 with the top two rows shown only.
lost due to leakage, we read the
entire memory, WL by WL, thereby
refreshing the data back into the
memory. It is interesting to know that
the interval between each two reads
for the same cell is around 32 ms. In
other words, the entire memory must
be read repeatedly in 32 ms intervals
(or 64 ms in more modern DRAMs).
The repeated refresh operation may
appear as too much housekeeping
but, given the speed of read access
(in the order of 100 ns), the refresh
operation turns out to take less than
1 % of the total time available for
memory operations.
There are many other subtleties
in the design of a DRAM that
go beyond the scope of this article.
However, it would be amiss not to
mention a few of them here.
1) Despite calling adjacent BLs BL
and BL in the folded-BL architecture,
the voltages on these two
lines are not complementary, as
you can verify from the timing
diagram of Figure 5.
2) The access transistor, being NMOS,
is a strong pull-down device, enabling
a strong read and a strong
write for 0, but not a strong pull-up
device to read or write 1. This means
if we need to store 1V (for 1) at the
storage node, we must raise the WL
above the Vdd
the case and is done by boosting
Vdd
either through a dedicated circuit
or through bootstrapping [4].
3) The SA is a differential amplifier,
but we typically capture its sensed
data from one side of it (say the
left side, connected to the BL). We
also write new data to the same
side of the SA and rely on the inverter
in the SA to produce the
data complement to drive the BL
This means that when we access
an even WL, we read the true values
of the stored bits, but when
we access an odd WL, we read the
complement values of the stored
bits. One may think of a simple
design that incorporates the least
significant bit of a WL address to
either flip or not flip the read bit.
However, this is not necessary
(continued on p. 83)
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
15
Time
tpre
tWL tSA Restore
level. This is indeed

IEEE Solid-States Circuits Magazine - Winter 2022

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