IEEE Solid-States Circuits Magazine - Winter 2022 - 33

the latch circuit is a digital circuit and
the distribution of the offset voltage
Vol
is large, an amplifier is often used
in the front stage of the latch. When
the gain of the amplifier is G, the
distribution of the offset voltage Vol
decreases to /VG
ol
at the input terminal.
However, since the distribution
of the offset voltage Voa
exists
in the amplifier, the linearity of ADC
deteriorates by this voltage distribution.
To obtain a DNL below onequarter
four least significant bits
(LSBs) for the quantization voltage
V ,q
Voa of V /6q
10V oa
or less voltage distribution
is required. For the 10-bit
flash ADC at a full-scale voltage of
., ,V
the voltage distribution of 160 μV
or less is required and this value is
fairly severe for normal devices.
To solve this problem, Figure 1(b)
was configured [1]. Reduce the number
of amplifiers and increase the
reference voltage between the amplifiers
to mV .q
the amplifier is connected by a circuit
the standard deviation of
Many analog-to-digital converters that I've
developed for digital video systems use
interpolation techniques.
in which multiple resistors are connected
in series, and the A/D conversion
value is obtained by comparing
the tap voltage of the resistor with a
latch. Figure 2 shows the output voltages
of the amplifiers and the voltages
of the resistance tap for the input voltage.
The voltage of the resistor tap is
the voltage that interpolates the output
voltage of a pair of amplifiers. The
polarity of the output voltage of a pair
of amplifiers is crossed by the reference
voltages Vra
and Vrb of the amplifier,
and the interpolation voltages Vra
and Vrb
cross at the input voltage that
The output voltage of
is evenly divided between them. Then
A/D conversion is possible in the configuration
of Figure 1(b).
The effect of each offset voltage on
the DNL Voe is expressed here. Here,
m is the reference voltage difference
between amplifiers normalized by
the quantization voltage :Vq
Voe
=+
'ccmm 1
m
V
oa
G
22 .05
Vol
.
(1)
Therefore, the voltage distribution
of the offset voltage Vol of the
latch does not change to /VG at the
ol
input terminal, but the effect of the
distribution of the offset voltage Voa
of the amplifier on the DNL is able to
reduce it to 1/m. Therefore, by using
this method, the effect of the offset
voltage Voa
of the amplifier on the
Amplifier
Comparator
Amplifier
G
Voa
Vq
G
Voa
Vol
mVq
Vpa
Vol
Vol
Latch
G
Voa Vna
Vol
Vpa
Latch
DNL can be suppressed, so that highprecision
flash ADC can be realized
even with a fine transistor that has a
large offset voltage distribution. Not
only the number of amplifiers with
large power consumption can be
reduced to 1/m, but also the use of
fine transistors is possible, resulting
in significant low power consumption.
The ADC using this method is
10-bit 300 MS/s ADC [1] using bipolar
transistors.
Generalization of
Interpolation Technique
The conventional A/D conversion is
performed by comparing the strength
of one signal with the reference
G
Vpb
Voa
Vol
Voa
G
Vnb
Vol
Vra
rb
Vpb
Input
V Vnb
(a)
(b)
FIGURE 1: (a) Flash ADC and (b) flash ADC using an interpolation technique.
Vna
FIGURE 2: Amplifier output voltages and
interpolated voltages for input voltage.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
33
Reference
Input
Clock
Reference
Input
Interpolation Resistors
Clock
Interpolated
Interpolated
IEEE Solid-States Circuits Magazine - Winter 2022

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