IEEE Solid-States Circuits Magazine - Winter 2022 - 34
The voltage of the resistor tap is the voltage
that interpolates the output voltage of a pair
of amplifiers.
voltage as shown in Figure 3(a). On
the other hand, A/D conversion using
interpolation is performed by dividing
the two signals a and signal b
evenly into m pieces. The intermediate
voltage x between signal a and
signal b based on the principle of
internal division is
x =
()
mk akb-+
m
,
(2)
where m is the number of divisions
and k is the weight. That is, the intermediate
voltage x is obtained by multiplying
the weight of (m-k) on the
Scale
(Reference)
5
6
7
4
Signal
1
2
3
(m - k)a + kb
(a)
x =
m
k
x
a
Signal
m
(b)
FIGURE 3: A/D conversion, using (a) conventional
and (b) interpolation techniques.
8
-∆V
4
TABLE 1. METHODS OF WEIGHTING.
■ Resistive interpolation: using resistors [1][2]
■ Capacitive interpolation: using
capacitors [3]
■ Gate-weighed interpolation: using
conductance of MOS linear region [4]
■ Time interpolation: using delay elements [5]
34 WINTER 2022
3
2
1
3
2
1
b
Signal
12
3
2
1
m-k
Course
∆V
Fine
3
2
1
12
8
4
Input
04 812
(b)
FIGURE 4: A two-stage A/D: (a) normal A/D conversion and (b) A/D conversion using
interpolation.
IEEE SOLID-STATE CIRCUITS MAGAZINE
Output
-∆V
4
3
2
1
12
8
3
2
1
∆V
3
2
1
signal a, adding the weight k to the
signal b, and normalizes it with m.
There are several ways to weight.
Table 1 shows methods of weighting.
Two-Stage Flash ADC
A flash ADC is not suitable for highresolution
ADC because the circuit
size increases in proportion to 2N
for resolution N, and not only the
area but also the power consumption
increases exponentially. Therefore, as
shown in Figure 4(a), if A/D conversion
can be performed in two stages;
upper stage and lower stage, the
number of comparators and power
consumption can be greatly reduced.
If the overall resolution is N and the
resolution of the subconversion is M,
the number of comparators n in the
ideal condition is
n=+ " @. (3)
-
22 2MN M
;E+
1 N
2
M=
N
2
When the resolution N is 10-bits, the
number of comparators can be greatly
reduced from 1,024 to 64 pieces to
1/16. However, there is a problem
that a large conversion error occurs
at the switching point of the upper
ADC due to the deviation of the
Course
Fine
3
2
1
12
8
4
Input
04 812
(a)
Output
Large Error
IEEE Solid-States Circuits Magazine - Winter 2022
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2022
Contents
IEEE Solid-States Circuits Magazine - Winter 2022 - Cover1
IEEE Solid-States Circuits Magazine - Winter 2022 - Cover2
IEEE Solid-States Circuits Magazine - Winter 2022 - Contents
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IEEE Solid-States Circuits Magazine - Winter 2022 - 3
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