IEEE Solid-States Circuits Magazine - Winter 2022 - 36

However, since the offset voltage is large,
the latch circuit requires a preamplifier, and
the low power and high accuracy are limited.
then also achieved 10-bits, it became
a trigger that greatly advanced the
low power CMOS ADC.
Interpolation With Gate Weights
A DVD recorder required a 7-bit
400-MS/s ultrahigh-speed ADC. An
ADC that requires ultrahigh-speed
operation with such low resolution
require a flash ADC, but power consumption
is large. A CMOS differential
latch that does not flow through
current is suitable. However, since
the offset voltage is large, the latch
circuit requires a preamplifier, and
the low power and high accuracy
are limited. Therefore, by using
the interpolation circuit shown in
Figure 1(b), low power consumption
and high accuracy can be
attempted, but power consumption
is an issue because of resistance
used for the interpolation circuit.
Then, the interpolat ion circuit
without the resistance was devised.
Figure 7 shows an ADC consisting
of a preamplifiers and latches for
the comparator.
Metal-oxide semiconductor (MOS)
transistors weighted-gate width W
are inserted on the source side of
the differential CMOS latch. Comparisons
can be made on the magnitude
of the conductors in the MOS linear
Comparator Latches With Gate
- Weighted Interpolation
CLK
regions of the left and right transistors.
The composed conductors of
each transistor are
G
=+aipT
ip
G
binT
in
=+n
n
L
C
6
11
^
WV V
WV V
^
22
where n is mobility, Cox
gate capacitance, VT
h
Th@
L
C
6 11
^
WV V
WV V
^
22
ox
h
Th@
ox
_
`
a
b
b
b
b
b
b
is a unit
is threshold
voltage, and L is channel length.
Therefore, the difference in composed
conductors is
GG
ab
-=
n ox
L
C
6
WV V
WV V
+^
-
^
11
1
22 2
ip in
ip in
h
h@ .
(5)
W1
Therefore, if the ratio of gate width
to W2
are
WW mk
-
12=
:: 1
m
m
k km
(6)
according to the principle of the
internal division shown in (2), it is
possible to compare the reference
voltages by m equality.
This latch has a large offset voltage,
but the offset voltage is reduced
to 1/G at the input end with the gain
of the preamplifier as G, and the
VDD
CLK
,
(4)
contribution of the preamplifier offset
voltage to DNL is reduced to 1/m, actually
1/8. The circuit in Figure 7(b) is a
dynamic circuit in which no through
current flows, and since the interpolation
resistor that consumes power
is not used, the power consumption
of the entire ADC is small. Therefore,
this ADC has a power consumption
of 50 mW at 450 MS/s, which is
10 times lower compared with other
ADCs and realizes low power consumption
that can be embedded on
the SoC for DVD recorder.
References
[1] H. Kimura, A. Matsuzawa, T. Nakamura,
and S. Sawada, " A 10-b 300-MHz interpolated-parallel
A/D converter, " IEEE J. SolidState
Circuits, vol. 28, no. 4, pp. 438-446,
Apr. 1993, doi: 10.1109/4.210026.
[2] A. Matsuzawa, M. Kagawa, M. Kanoh, K.
Tatehara, T. Yamaoka, and K. Shimizu,
" A 10 b 30 MHz two-step parallel BiCMOS
ADC with internal S/H, " in Proc. 1990 IEEE
Int. Conf. Solid-State Circuits, pp. 162-163,
doi: 10.1109/ISSCC.1990.110177.
[3] K. Kusumoto, A. Matsuzawa, and K. Murata,
" A 10-b 20-MHz 30-mW pipelined interpolating
CMOS ADC, " IEEE J. Solid-State
Circuits, vol. 28, no. 12, pp. 1200-1206,
Dec. 1993, doi: 10.1109/4.261992.
[4] K. Sushihara and A. Matsuzawa, " A 7bit
450MSPS 50mW CMOS ADC in 0.3 mm2, "
in Proc. IEEE Int. Solid-State Circuits Conf.,
Tech. Dig. Papers, 2002, pp.170-171, doi:
10.1109/ISSCC.2002.992990.
[5] M. Miyahara, I. Mano, M. Nakayama, K.
Okada, and A. Matsuzawa, " A 2.2GS/s 7b
27.4mW time-based folding-flash ADC
with resistively averaged voltage-totime
amplifiers, " in Proc. IEEE Int. SolidState
Circuits Conf., Tech. Dig. Papers,
Feb. 2014, pp. 388-389, doi: 10.1109/
ISSCC.2014.6757482.
Pre-Amplifiers
Reference
Input
(a)
Vi1p W1
Ga
W2Vi2p Vi1n W1
Gb
W2 Vi2n
About the Author
Akira Matsuzawa received his B.S.,
M.S., and Ph.D. degrees in electrical
engineering from Tohoku University,
Sendai, Japan, in 1976, 1978, and 1997,
respectively. In 1978, he joined Panasonic.
Since then, he has been working
on R&D of analog and mixed-signal
large-scale integration technologies;
video-rate ADCs, CMOS sensors, RF
CMOS circuits, and MS SoC for DVD
systems and low power technology.
In April 2003, he joined Tokyo Institute
of Technology as a full professor.
He researched millimeter-wave CMOS
TRX and advanced ADCs.
In March
Gate-Weighted Interpolation
(b)
FIGURE 7: (a) ADC and (b) a latch circuit with gate-weighted MOS [4].
36 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
2018, he became a professor emeritus,
and founder and CEO of Tech Idea Co.,
Ltd. He is Fellow of IEEE.
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