Athanasios Ramkaj, Marcel J.M. Pelgrom, Michiel S.J. Steyaert, and Filip Tavernier In the Pursuit of the Optimal Accuracy-Speed- Power Analog-to-Digital Converter Architecture A mathematical framework T he everlasting challenge in the design of every analogto-digital converter (ADC) lies in maximizing the accuracy·speed÷power product by pushing all metrics toward their desired directions. To this end, tremendous progress has been made in advancing ADC performance both circuit- and architecture-wise. These advances have been captured by means of comparing experimental data points in surveys, with [1] being the most noteworthy. However, such comparisons give an ill-defined view since the data points correspond to different architectures that were optimized under different constraints and implemented in different process nodes. This provides little insight on architectural limits and makes a direct comparison under similar assumptions nontrivial. This article introduces a mathematical framework to systematically estimate and compare the accuracy-speed-power limits of different ADC architectures with a complete decomposition of the blocks' contributions. (Speed refers to both sample rate and bandwidth in the sense that they are tightly coupled, Digital Object Identifier 10.1109/MSSC.2021.3128310 Date of current version: 24 January 2022 1943-0582/22©2022IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022 45