IEEE Solid-States Circuits Magazine - Winter 2022 - 48

The SAR accuracy-speed-power
Vin
S/H
Vsh +
-
VDAC
DAC
B
B-bit SAR Logic
FIGURE 3: A B-bit SAR ADC.
P ,F lad is derived by considering the
static power through the ladder with
a resistance sized for a portion of the
total noise budget
PVDD
F,lad
=
=
VDD
$
$
c
e
$ ^{sup
{supVDD
R
lad
V
4
,
DDh ,
m
kT j samp $ f
$
VRlad
Fs
2
o
(9)
where it is assumed that the integration
noise bandwidth is equal to the
1 /fs
pler. Finally, P ,F dig
fraction allocated to the samis
computed by
estimating the number of minimumsized
gates necessary for the encoder.
Assuming a Wallace encoder as in
[2] running at
f ,s
Fs
PV fB CV52
,min
dig=-^h
B
DD $$ $$ $
DD
(10)
SAR Accuracy-Speed-Power Limits
The SAR ADC relies on a bit-at-a-cycle
approximation of the input signal [8],
[9]. Its basic components (Figure 3)
are the S/H to sample the analog input,
the DAC to give binary-weighted
references, and a comparator to
evaluate the difference between the
sampled input and the DAC output.
Different topologies exist for the
DAC, with the CDAC currently prevailing
owing to its merging ability
of the S/H and DAC functions,
its
dynamic nature, and its superior
linearity over its resistive or currentsteering
equivalents. Several switching
schemes exist [10], which are not
detailed here for the sake of brevity.
The SAR logic collects the bits
and stores the comparator decision,
based on which it generates the next
48 WINTER 2022
PV fSS s,, >* 1 - 2 V Ssj comp $ f 4
min, T
comp = DD j comp
+
Z
[
\
]
]
]]
$$ $
BA 2
2
h
1 -
6^ -+ @ max " CC VGT
6^ -+ @ jSs
loglnlnBER-1
Ih $
BA 2
r
2IL min,
loglnlnBER-1
,
$
,comp $ f
fT
$$ $
T
max " CC V
,
$
,
rV
GT
I
$
fT
2
_
`
a
b
b
bb
V
X
W
W
W
W
,
(13)
II
reference to minimize the difference
at the summing node,
V .res During
conversion, the full range is divided
by 2 in every cycle by appropriate
grouping of the DAC elements. After
sufficient DAC settling, the comparator
evaluates the polarity between
Vsh
Dout
Incorporating the parasitic loading and
process effects described in the previous
section, " SAR Accuracy-Speed-
Power Limits, " P ,S samp
and P ,S comp
their final forms as follows:
PV NTCf
CC
" SI I
and VDAC and outputs the first CVDDh
$
minsup
1E ^{
we get the following:
.
bit. The procedure continues until
all bits are evaluated, and the B-bit
output is collected. In contrast to the
flash, the SAR resolves B bits in B
cycles, but with minimum hardware.
The SA algorithm is not limited to binary
weights, and the input can be
still approximated within a given accuracy
with nonbinary (<2) weights,
but with extra cycles.
Despite the remarkable efficiency
of the SAR for low-medium resolution
and megahertz speeds [Figure 1(b)],
its bit/cycle nature remains the main
bottleneck in greatly extending the
speed of this converter while preserving
its efficiency. Several speed-boosting
techniques have been proposed to
tackle this bottleneck [9] but are out
of the scope of this article. Further,
when the resolution increases above
10 bits, driving the noise-limited input
capacitance at gigahertz speeds
with low noise and distortion, highenergy
efficiency becomes extremely
challenging.
,,
,
min,+max'AC c
jSs
rfT
,comp $ f
m
(12)
and in (13), at the bottom of this page,
where
^h+ bb capture
the /f1-period
B 11 07 05
s
B 1
$$
jS,samp =+ and jS ,comp
$ /, ..
=
fraction given to the
sampler and comparator, assuming a
synchronous ADC with smart comparator-CDAC
time-sharing [9].
For
P ,S CDAC a symmetrical energy,
saving
switching is assumed [9], [10].
The reference,
V ,REF
is provided by
a regulating circuit drawing current
from VDD
mre ,f
leading to
P CDAC = VDD
$$ -
j
B
$$
ma ,.x
/ ^h
'
=
-
1
1
22 1
2
Bj j
-32
C
CV (14)
min1
B
S
REF
The above gives the average switching
over a full ADC period, and
//
jb$=+
6^^ -hh@
S,CDAC
BB
11 1
considers
the comparator-CDAC timesharing.
A value of 60% is assumed
SS s$$f
mref
,,
j CDAC
with an efficiency factor,
SS s ;max,,$ j samp
samp = DD
$$ $
$
Vres
limits are derived by estimating the
power consumption of a binaryweighted
synchronous converter, including
sampler, comparator, CDAC,
and SA logic contributions
PP BP=+ $
+ P
.
SS SS
S
,, ,,
,
totsampcompCDAC
dig
+ P
(11)
take
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IEEE Solid-States Circuits Magazine - Winter 2022

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