IEEE Solid-States Circuits Magazine - Winter 2022 - 50

Vin
S/H1
+
-
DAC1
SAR1 Logic
Residue
Amplifier
B1
B2
B
Align and Combine
FIGURE 5: A B-bit 2-stage pipelined-SAR ADC.
found as in (5) by considering also
the RA settling, resulting in
PV NTCf
CC
PP s
S
,,$ j samp
samp = DD
"
$
$
c
e
,
,comp $ f
jPs
rfT
CVDDh.
minsup
1E ^{
$
To derive P ,P comp,tot
,
min, 21
m,
+- h
min1+
^
Bs
j RA BB 12 2 f
Ps s
set $
, $$ $
gr T
^ -- + h ln
^
h
CAC
f
max
max
'
s
$$ $
$
'AC
;max
II
RA
o,
(19)
the 2×-redundancy
is considered for absorbing
errors, thus relaxing the comparator

IEEE Solid-States Circuits Magazine - Winter 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2022

Contents
IEEE Solid-States Circuits Magazine - Winter 2022 - Cover1
IEEE Solid-States Circuits Magazine - Winter 2022 - Cover2
IEEE Solid-States Circuits Magazine - Winter 2022 - Contents
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IEEE Solid-States Circuits Magazine - Winter 2022 - Cover3
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