IEEE Solid-States Circuits Magazine - Winter 2022 - 51

P ,PS samp is derived including all the
aforementioned laid-out assumptions
and effects
PV NTC
fCCAC
jPS,comp $ fs
PS samp = DD
"
$$
$
$
c
e
rfT
,,$
;
sS II
maxmax
max
,
jPS ssBB 12 2 f
RA -- +
set $
, $$ $
gr T
^^
m
CVDDh.
min1E ^{sup
$
hh ln
,
CAC
f
min,+
min1+
'
s
'
RA
o,
(23)
In our pipelined-SAR derivation, we
allocate one and a half cycles to both
the sampler and the RA, captured by
,/..
jj RA=+ +^h This
PS,,PS
samp
B 12 15
s
is effectively seen as fitting one extra
cycle in the total /,f1-period
B 12 1 /.
s
jb$=+ +^h
P ,,PS RA tot
PS,comp
s
assumes the same g Cm,RA
RA
circuit with all the assumptions and
effects already discussed as shown in
(24) at the bottom of this page.
One distinct difference regarding
the RA gain between the pipeline and
pipelined-SAR is that in the former,
As
remains constant when increasing
B since Bs is constant, whereas in the
latter, As is a function of Bs
since the
bit partitioning is not the same when
increasing B.
P ,PS comp,tot
P ,P comp,tot by substituting ,P compj
with jPS,comp
. For P ,,PS CDAC tot
,
the
same switching as in (14) is considered
with the appropriate sub-SAR
switching activity, depending on the
bit partitioning. Further, considering
all stages under study, as well as the
stage scaling, we get
PPS DAC,tot = VDD
mref
5
$$ #
$
)
//
%
i=2
e
C
2 s^ h
Bi
S
Bi jj
^
s --^ h 32
j=1
4
=0
l AB i^^ hh
sl
1 CVREF
s
,.
min3G
(25)
PA Bfs
gset
PS RA tot = ssh$$ $
,,
#$22-i=0
=
"" G,,minmin
m 2
//
^
jPS,RA
-
maxmax $$ $
i=0
Bi
Bi
in,I
CC CC VV
1
-AB h $
m 2
ss
^
-
RA ,, .
2hlin
^^ 1ss DDhh GT
--1$$+
(24)
^BBs
^BBs
-- +
-- +
^
^
12 2
12 2
h
h
r
h $
h $
ln
ln
$
jPS,RA $ fs
gset $ fT
,,
s^ h 1
$$fs
jPS CDAC
= 22 1- ho max
Bi -
is identical to (20) for
with
Pipelined-SAR
$ jPS samp
TABLE 1. NOISE ALLOCATION PERCENTAGE (%) WITH RESPECT TO A CERTAIN
TOTAL QUANTIZATION NOISE,
fq
Full flash
Binary SAR
Pipeline
SAMPLER
50
50
40
40
A 1sl
=
2 .
COMPARATOR
35
50
15
20
In the above, l 0= corresponds to
the CDAC of the first stage (),
while the CDAC timing portion over
a full converter period is captured by
// .
asjb$=+
+-6^^hh@
To conclude our derivations, P ,PS dig
PS, ssCDAC
BB
12 11
sumes the same number of gates for
each sub-SAR as for the regular SAR
and adds two extra gates per bit in
each for the align and combine logic
PV fB B
CV
$$ DD .
PS ss s
,dig=+^hDD 52$$ $$
min
(26)
Putting It All Together
To build insight on the discussed
architectures' strengths and limitations,
these are compared in terms
of their accuracy-speed-power
limits derived through (1)- (26)
and plotted in Figure 6. Four deepscaled
CMOS processes are used,
and the critical parameters are extracted
from core low-threshold
devices with interconnect. Cmin
is
extracted as a 2×-minimum-sized
inverter gate capacitance with equal
PMOS/NMOS drivability. The allocated
noise percentage to set the
corresponding capacitors-
C ,L and CRA
C ,S
C ,I
For low speed [;f 500kHz Fig-are
given in Table 1.
s =
ure 6(a)], the slopes of all the curves
are first process-limited, with Cmin
setting the baseline, and then noise
limited. Above about 40 dB SNDR,
flash becomes the most energy inefficient,
with a slope
\2 .B
The pipelines
RA
-
-
40
40
LADDER
15
-
5
-
show a similar slope when noise-limited
but with a better overall efficiency
owing to redundancy. The SAR
is very hard to beat up to about 45 dB,
after which its energy increases
with a slope
\B . The pipelined-SARs
follow similar noise-limited slopes,
showing the best efficiency between
45 and 65 dB while being slightly
more efficient than the multibit/
stage pipelines up to 70 dB. For medium-high
speed [;M
f 500Hz Figs
=
ure 6(b)], the flash remains the most
inefficient above 40 dB. The others
show steeper relative slopes owing to
more stringent internal timings and
increased parasitic effects through
/.
ff The SAR is still superior up to
sT
40 dB. The fewer-stage pipelines and
pipeline-SARs start losing the battle
at high accuracies because the relaxed
RA precision benefit is offset by
the higher gain-bandwidth requirement.
The 1,2-bit/stage pipelines and
the 4,5-stage pipelined-SARs lead the
efficiency at accuracies above 75 dB.
For very high speed [. ;
f 13GHz
s =
Figure 6(c)], the flash remains almost
intact, while the exacerbated parasitic
contribution in the others further
deteriorates their efficiency. The SAR
retains the lead up to 40 dB, while
the 1,2-bit/stage pipelines lead above
75 dB. The 4,5-stage pipelined-SARs
are winning between 40 and 65 dB
and compete with the pipelines up to
75 dB. Extending the pipelined-SAR
beyond five stages may even surpass
the 1-bit/stage pipeline efficiency
when targeting multi-gigahertz-range
speed. For a similar stage count, the
pipelined-SAR is potentially more efficient
and faster than the pipeline
for an extended range of accuracies.
For each architecture, the derived
limits are very similar across the
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
51
IEEE Solid-States Circuits Magazine - Winter 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2022
