IEEE Solid-States Circuits Magazine - Winter 2022 - 57

of signal-to-noise and distortion ratio
(SNDR) to give a measure of ADC power
efficiency. Note that a lower P/fsnyq
metric represents a more efficient
circuit on this chart. For low-to-medium-resolution
converters, energy is
primarily expended to quantize the
signal; thus, the overall efficiency of
this operation is typically measured by
the energy consumed per conversion
and quantization step. The dashed
trend line represents a benchmark
of 1 fJ/conversion step. Circuit noise
becomes more significant with higherresolution
converters, necessitating a
different benchmark proportional to
the square of the signal-to-noise ratio,
represented by the solid line. Designs
published from 1997 to 2021 are
shown in circles. ISSCC 2022 designs
are shown in black dots.
Figure 4 plots the signal fidelity
versus the Nyquist sampling rate normalized
to power consumption. At
low sampling rates, converters tend
to be limited by thermal noise, independent
of the sample rate. Higher
speeds of operation present additional
challenges in maintaining accuracy
in an energy-efficient manner, indicated
by the roll-off versus the frequency
in the dashed line. The past
10 years have resulted in an improvement
of more than 10 dB in powernormalized
signal fidelity, or a 10×
improvement in speed for the same
normalized signal fidelity. At this
year's ISSCC, audio delta-sigma converters
reach new levels of efficiency,
while no less than four pipelined-SAR
converters continue the trends in the
speed-versus-efficiency corner of the
graph. Noise-shaping SAR converters
show their strengths in high-efficiency
and high-speed converter design.
Figure 5 graphs the ADC bandwidth
as a function of the SNDR. Sampling
jitter and aperture errors coupled with
an increased noise bandwidth make
achieving high resolutions and bandwidths
a particularly difficult task.
Ten years ago, a state-of-the-art data
converter showed an aperture error of
approximately 1 psrms, and in recent
years, designs with aperture errors
below 100 fsrms have been published,
many of which have been published at
ISSCC. Finally, this year's ISSCC presents
two converters advancing the
state of the art in incremental converter
design, showing the strength of this
architecture for the extremely efficient
and very small converters required for
IoT applications.
Communication Systems:
Radio-Frequency Subcommittee
Subcommittee Chair: Jan Craninckx,
IMEC, Leuven, Belgium
ISSCC 2022 features record-setting
advances in phase-locked loops
(PLLs), voltage-controlled oscillators
(VCOs), power amplifiers (PAs),
radio-frequency (RF) front-end cir190
180
170
160
150
140
130
120
cuits,
and terahertz prototypes
driven by emerging requirements
in 5G and 6G communication, radar,
and imaging. While 5G applications
show advances in linear operation,
high average efficiency, and duplex
operation at 28 and 39 GHz, remarkable
achievements are also demonstrated
in frequency bands above
100 GHz to improve output power
and efficiency. Additionally, circuit
improvements based on advanced
CMOS processes benefit existing
systems, such as Wi-Fi and low-power
IoT devices.
Frequency Generation
ISSCC 2022 highlights the improved
performance of VCOs and features
ISSCC 1997-2021
Envelope
ISSCC 2022
1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12
fsnyq (Hz)
FIGURE 4: The power-normalized noise and distortion versus the Nyquist sampling rate.
1.E+11
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
ISSCC 1997-2021
Jitter = 1 psrms
Jitter = 0.1 psrms
ISSCC 2022
10 20 30 40 50 60 70 80 90 100 110 120
SNDR at fin,hf (dB)
FIGURE 5: The bandwidth versus the SNDR.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
57
fin,hf (Hz)
FOMs,hf (dB)
IEEE Solid-States Circuits Magazine - Winter 2022

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