IEEE Solid-States Circuits Magazine - Winter 2022 - 58

The need to faithfully preserve a signal across
domains continues to pressure data converters
to deliver more bandwidth and linearity.
several approaches that demonstrate
a -190 dB relative to the carrier (dBc)/
Hz figure of merit (FoM). First, a
10-GHz series-resonance oscillator
achieves a phase noise of -138 dBc/Hz
at a 1-MHz offset, and second, a 60-GHz
multicore oscillator achieves a phase
noise of -136 dBc/Hz at a 10-MHz
offset. A triple-core VCO further advances
the FoM through a broadened
tuning range that leverages multiple
resonances. New advances in
terahertz bands for imaging based
on coupled-oscillator arrays with p-in
diodes for harmonic generation increase
the tuning range and RF-to-dc
efficiency over prior art.
This year's ISSCC also introduces
PLL concepts for generating RF, microwave,
and millimeter-wave (mm-wave)
frequency carriers, with several lowjitter
and low-power prototypes that
ultimately push the jitter power FoM
below -250 dB, as presented in Figure
6. PLL advances include a variety of
subsampling and digital approaches in
fractional-N architectures. A fractionalN,
type 1 sampling PLL based on a voltage
interpolator exhibits an accelerated
start-up with a crystal oscillator. Breakthroughs
in all-digital PLLs for radar offer
a phase noise of -120 dBc/Hz at
1 MHz, and low frequency modulation errors
are shown. A 5-nm, fin field-effect
transistor (FinFET), CMOS, cascaded PLL
achieves a
204-fs rms
jitter and -241-dB
FoM with wideband operation. An
ultralow-jitter, fractional-N, ring oscillator
(RO), digital PLL dynamically selects
a phase sector to reduce the digital-totime-converter
range and thermal noise
for a
188-fs rms
jitter and -243-dB FoM.
A fractional-N, digital PLL employs
a time mode arithmetic unit to perform
time estimation and amplification
tasks, with a -249.4-dB FoM. An
RO-based, injection-locked, digital
PLL incorporates a reference octupler
with probability-based adaptive calibration
to achieve a
177-fs rms jitter.
A harmonic mixing-based, fractional-N
PLL with a coupled mm-wave
VCO achieves an
88-fs rms jitter and
-250-dB FoM. A 28-nm, fractional-N,
bang-bang PLL achieves a
68.6-fs rms
jitter. Finally, a 25.8-GHz, integer-N
PLL with a time-amplifying phase frequency
detector suppresses charge
pump noise to reach a
60-fs rms
jitter
and -252.8-dB FoM. These integer-N
and fractional-N PLLs continue to
improve power consumption and
integrated jitter to keep pace with advances
in communications and sensing
applications.
RF and mm-Wave PAs
This year's conference will introduce
several exciting PA innovations
spanning RF bands below 7 GHz to
terahertz bands extending to 425 GHz.
These innovations improve the efficiency,
output power, linearity, and
bandwidth of PAs and front-end
components. ISSCC 2022 will showcase
record-setting work in frequency
bands above 100 GHz, including
1) a silicon-germanium (SiGe) prototype
of a Doherty PA demonstrating
an average efficiency of 12% and 2) a
CMOS PA with 1.6 W of output power
through massively scaled powercombining
networks. As shown in
Figure 7, these demonstrations establish
new benchmarks for siliconbased
technologies above 100 GHz.
Other exciting developments for
1,000
100
10
0.001
0.010
0.100
1
FoM -220 dB
FoM -210 dB
FoM -200 dB
ISSCC 2022
FoM -230 dB
FoM -240 dB
FoM -250 dB
PAs include a multiband digital PA
realized in a 16-nm FinFET process
that achieves a power of 28 db/mW
(dBm) for emerging 6-7-GHz applications,
a bulk CMOS PA using a threeway
Doherty architecture to achieve
high average efficiency for high backoff
signals that reaches 25.5 dBm at
28 GHz, and a compact, wideband,
bidirectional front end that achieves
high efficiency and low noise while
operating without a transmit/receive
switch. Other remarkable concepts
are presented in RF front-end components,
including an accurate power
and impedance detector for load impedance
sensing at the antenna
in a phased array and a broadband
(1-18-GHz) silicon mixer and an integrated
local oscillator driver with a
P1dB
FoM -260 dB
exceeding 20 dBm.
FoM -270 dB
Communication Systems:
Wireless Subcommittee
0.1 110
Power (mW)
FIGURE 6: The PLL trends.
58 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
100
Subcommittee Chair: Stefano Pellerano,
Intel, Hillsboro, Oregon, USA
The continuing demand for higher
wireless data rates in the context
Jitter2 (ps2)
IEEE Solid-States Circuits Magazine - Winter 2022

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