IEEE Solid-States Circuits Magazine - Winter 2022 - 61

Tx building blocks are implemented in
CMOS technology.
Scaling Electrical Interconnects to
100 Gb/s and Reaching >200 Gb/s
Bandwidth requirements in data centers
and telecommunication infrastructure
continue to drive the demand for
ultrahigh-speed wireline communication.
Over the past few years, complete
Txs operating up to 112 Gb/s were
demonstrated across a long-reach copper
channel with a >45-dB loss. Two
notable trends in these Txs, especially
for long-reach channels, are the adoption
of PAM-4 modulation and a transition
to DAC/ADC architectures with
digital signal processor (DSP)-based
equalization. Although PAM-4 provides
twice the data rate at the same
baud rate as conventional NRZ to relax
channel loss requirements for bandwidth
doubling, it also comes with
more stringent requirements for linearity,
noise, and multilevel signaling.
This trend has motivated development
of low-power data converters, digital
equalization, and clock recovery along
with linear, high-bandwidth Tx and
Rx analog front ends. Over the past
two years, the first components were
demonstrated to extend these Txs to
112 Gb/s. This year, ISSCC includes an
implementation of a 112-Gb/s, PAM-4,
long-reach Tx in 5-nm CMOS with relatively
low power consumption.
In paper 6.2, Marvell describes a
112-Gb/s, PAM-4 Tx for long-reach
copper interconnects consuming
only 4.5 pJ/b while operating over
a channel with a 50-dB loss. In addition,
Peking University (paper 6.3)
presents a 112-Gb/s, PAM-4, mixedsignal
Tx design in 28-nm CMOS,
which achieves a 10-11 bit error rate
(BER) over a 20.8-dB loss channel,
while consuming 2.29 pJ/b. While
112-Gb/s links are maturing, several
papers at ISSCC are directed to doubling
the data rate to 224 Gb/s. In
paper 6.1, Intel demonstrates a first
224-Gb/s, PAM-4, ADC-based Rx consisting
of an inductively peaked analog
front-end, a 64-way interleaved
ADC, and a DSP incorporating a 16-tap
digital feed-forward equalizer. The
power efficiency of the analog part is
1.41 pJ/b over a channel with 31 dB. In
paper 17.4, the University of California,
Los Angeles also demonstrates a 56GHz,
fractional-N PLL in 28-nm CMOS
for 224-Gb/s PAM-4 transmitters.
Short-Reach Links for Intrapackage
Communications
As a consequence of the increasing demand
for bandwidth in high-throughput
systems used in AI, HPC, and switch
applications, multiple devices are integrated
in the same package, and data
are sent between chips in the same
package or between a central chip and
copacked optics. For these applications,
relatively short distances
1,000
100
10
1
110
Process Node (nm)
FIGURE 11: The data rate versus the process node and year.
100
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
(<50 mm) have to be bridged with minimum
power and at the highest throughput
per millimeter chip edge (Gb/s/mm).
Since the channel attenuation and discontinuity
in these links are small, lowpower,
analog-oriented architectures
are preferred over heavy DSP-based solutions
for longer channels. In paper
6.5, Marvell presents an 8 × 113-Gb/s,
PAM-4 extra short reach Tx in 5-nm
CMOS, which achieves a 10-11 BER over
an 80-mm multichip module channel
while consuming only 1.55 pJ/b.
Optical Links for Upcoming 400-Gb
Data Center Interconnects
The explosive growth of data and
datacentric computing places stringent
1,000
Other
ISSCC 2022
100
10
1
0.1
02040
Channel Loss at Nyquist (dB)
60
FIGURE 12: The power efficiency versus the channel losses at the Nyquist frequency.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
61
Data Rate (Gb/s)
Power Efficiency (mW/Gb/s)
IEEE Solid-States Circuits Magazine - Winter 2022

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