IEEE Solid-States Circuits Magazine - Winter 2022 - 62

demands on the bandwidth and energy
efficiency of data center interconnects,
spurring the development
of several 200-400-Gb Ethernet standards.
Low-power data converters
and optical integration are the two
key components for the development
of high-performance, optical, pluggable
modules using coherent detection.
In paper 17.1, Peking University
presents a first 200-Gb/s, analog,
dual-polarization quaternary phaseshift
keying, coherent, optical Rx
in 28-nm CMOS, which achieves a
4.6-pJ/b power efficiency with an
active area of ..
006mm2
The Rx
is based on 12-MHz carrier recovery,
equalization for 10-km optical
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Year
2014 2016 2018 2020 2022
FIGURE 13: The core count trends (a red diamond designates a multichip module).
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FIGURE 14: The die counts in system trends.
62 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
2020
2022
transmission, a 1.2-Mrad/s state of
polarization, and a 9-dB electrical
channel loss.
While coherent optical communication
covers long distances, demand
is also surging for shorter, noncoherent
(<2 km) optical links. Several
400-Gb Ethernet standards (e.g., 400-Gb
DR4/FR4) target optical line rates of
100 Gb/s. Since these links are envisioned
to be employed in data centers
in high volume, low cost and low power
are key requirements. Solutions have
typically employed an analog PAM-4
optical transmitter utilizing a microring
or traveling wave Mach-Zehnder
modulator, which results in high power
dissipation and a large area and significant
cost. In paper 17.2, the California
Institute of Technology demonstrates
an optical, 100-Gb/s, PAM-4 transmitter
in a SiP-CMOS platform, including
a push-pull segmented MZM structure
using MOSCAP phase modulators. The
driver IC is implemented in 28-nm
CMOS and consumes only 2.4 pJ/b.
Concluding Remarks
Continuing to aggressively scale IO
bandwidth is essential for the industry,
but the tradeoffs between bandwidth,
power, area, cost, and reliability
are extremely challenging. Advances
in circuit architecture, interconnect
topologies, transistor scaling, and integrated
silicon photonics are changing
how IO will be done over the next
decade. The most exciting and promising
of these emerging technologies
for electrical and optical interconnects
will be highlighted at ISSCC 2022.
Digital Systems: Digital
Architectures and Systems
Subcommittee Chair: Thomas Burd,
Advanced Micro Devices, Santa
Clara, California, USA
This year's selection of processor
papers highlights the industry trend
toward multidie integration in a
package with increased numbers of
transistors per system. Innovative
packaging technologies, including 3D
stacking and direct bonding, are being
productized, which supports the
easy integration of multiple process
nodes into a single socket (Figures 13-
15). This has also fueled an exponential
increase in on-system memory
that drives increased performance
(Figure 16). The drive to higher clock
frequencies has plateaued, replaced
by a drive to increased core counts.
Bump and through-silicon-via pitches
continue to scale down at a rapid
rate, enabling a tremendous increase
in bandwidth across multiple dies.
The mobile CPU continues to increase
in both frequency and performance,
while providing a wide range of functional
and energy efficiency. The system
scalability trend is also evident
in a configurable array of processing
Die Count
Cores
IEEE Solid-States Circuits Magazine - Winter 2022

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