IEEE Solid-States Circuits Magazine - Winter 2022 - 8

called a " run. " Consider the input
waveform shown in Figure 2(c), where
a zero and two ones occur between
t1
and t .4 From the first bit, the DFE
generates a feedback value of - h1
and subtracts it from the second
bit, yielding
su 1
m
Dh .1=+ Next, the
circuit generates DhF =+ 1 from B2
and subtracts it from B ,3 degrading
1 h .1
the swing to - This is the price
paid for dealing with the eye closure
due to a 1010 sequence.
The channel impulse response de -
picted in Figure 1 exhibits higher postcursors
as well. We can then employ
additional FFs and feedback taps to
cancel those components. The total
number of taps depends on the type
of the channel and is typically in the
range of five to 10 [2].
The principal challenge in DFE de -
sign relates to the finite delay around
the loop. If excessive, this delay simply
causes the circuit to fail. As explained
in [7], the following timing constraint
must be met:
TT ,TTCK QFBsetup
- ++ # b
where T ,CK QT
,FB and Tsetup
(1)
denote
the FF clock-to-Q delay, the feedback
delay, and the FF setup time,
respectively. These quantities can
be reduced by means of inductive
peaking at the summing junction
FF1
First
Latch
Din
+
-
CK
DF
B1
+1
Din
t1
-1
+h1
DF
-h1
+1
Dsum
-1
t2
(b)
t3
-1 - h1
(c)
FIGURE 2: (a) The basic DFE topology as well as its effect with a (b) 1010 sequence and
(c) 11 run.
Dsum
+∆V
t1
-∆V
FIGURE 3: The typical waveform at the summing junction.
8
WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
t2
t3
t
Tb
t
-1
t2
t3
t
1 + h1
Dsum
t2
t3
t4
DF
t2
t3
t
-1
+h1
-h1
+1
1 - h1
t
-1 - h1
t2
t3
t4
1 + h1
t
Din
t1
t2
t3
t4
t
B2 B3
+1
h1
(a)
B1 B2 B3
The noise and offset voltages must
be calculated for a particular CTLE/
DFE cascade, but we typically target
a VT
of at least 150-200 mV to
accommodate the FF's finite sensitivity
as well [6]. We return to this
point later.
Numerous DFE architectures have
been reported [2]-[8], and the pros
and cons of some have been described
in [7]. Most do not relax the timing
constraint expressed by (1). We begin
with the full-rate, " direct " topology of
Figure 2(a) for its simplicity and consider
others if this approach does not
provide satisfactory performance.
Channel-CTLE Impulse Response
To compute the relative strengths
of the DFE taps, we must examine
the impulse response of the channel-CTLE
cascade. We apply to the
channel a differential pulse having
a width of 2 ps (. )
% =bT 17 9ps
and
rise and fall times of 0.1 ps. Plotted
in Figure 4 are the output waveforms
of the channel and CTLE. The former
exhibits its first, second, and
CK
Dsum
A
DM
L1
L2
Dout
Second
Latch
and within the FF but at the cost of
greater complexity and signal-routing
difficulties.
The overall equalizer BER is determined
by the eye opening at the summing
junction, node A in Figure 2(a).
Illustrated in Figure 3 is the waveform
at this node, exhibiting a worstcase
peak of
TV . Sensing this voltage,
the FF must make correct decisions
in the presence of two nonidealities:
the total root-mean-square (rms)
noise V ,rmsn
V ,OS
both referred to this interface.
The noise and offset contain contributions
by the CTLE, summer, and
FF. For
BE 10-12 , we write
R.
2
1
Qcm -12
- 4
TVVOS
V
nr, ms
where ()Q $
is the " error function "
(the integral of a Gaussian distribution).
Note that V4 OS
represents the
4v variance of the offset. This condition
is satisfied if the argument of
Q ()$
exceeds seven, i.e., if
T $
VV V74,nrms
+
OS
.
(3)
110
,
(2)
and the total dc offset
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