IEEE Solid-States Circuits Magazine - Winter 2022 - 9

third postcursors at relative levels of
60%, 41%, and 30%, respectively. The
latter indicates that the CTLE reduces
these to 22%, -3%, and -6%, respectively.
The slightly underdamped
response at the CTLE output originates
from a few decibels of peaking
that appear in the cascade frequency
response (shown in the first article
in this series [1]).
The voltage swings in Figure 4 characterize
the CTLE under small-signal
conditions. This is necessary because we
can predict the step or pulse response
from the impulse response only if the
system remains linear. Also, the worstcase
scenario of a 1010 sequence does
lead to relatively small swings at the
channel output. Nevertheless, as the
channel and CTLE " recover " from a long
run, e.g., between t1
and t2
in Figure 3,
dynamic nonlinearities in the CTLE can
cause departure from our foregoing
results. In other words, some iteration
in the DFE tap values may be necessary
if the greatest eye opening is desired.
FF Design
The performance of the DFE shown
in Figure 2 hinges primarily upon
the FF design. While the simplicity
and efficiency of the StrongARM
latch make it a desirable candidate
here, we recognize from (1) that
the FF delay must remain below
T .,17 9ps
b =
typically chosen in the range of 400
to 500 mV. With complete switching
of M1
ual to1m R ,
R 500 .
D
M4
-M ,4 these swings are eq -
A D
# suggesting
. X We must also
ensure that the small-signal
loop gain around M3
and
is greater than unity
so that the circuit properly
regenerates when CK falls
and CK rises.
The clock path in
erate gate-source voltage, e.g., around
700 mV, so that these transistors
operate in or near saturation. Third,
the current mirror as
well as C1
and C2
To compute the
relative strengths
of the DFE taps,
we must examine
the impulse
response of the
channel-CTLE
cascade.
Figure 5 merits some re -
marks. First, at 56 GHz,
CK and CK are close to sinusoids, especially
if they are provided by resonant
buffers (stages with LC tank loads).
Compared to square waves, sinusoidal
clocks exhibit longer transition times,
thus elongating the FF response. Second,
if nearly rail-to-rail clock swings
are available, then C1
and C2
need
not be much greater than the input
capacitance of M5
and M .6 This is
because we prefer to maintain a modcan
be
shared among all of
the DFE's latches; the
capacitor values are then
chosen according to the
total gate capacitance that
they must drive.
When characterizing
the speed of FFs for a DFE
environment, we should
examine their input sensitivity
V ,sen
defined as the minimum difference
that guarantees correct decisions
at the desired clock frequency. Specifically,
Vsen
must be studied in the
context of the waveforms delivered
by the channel-CTLE cascade, e.g., a
1111 run followed by a 0101 pattern
(Figure 3). The swing received by the
FF after the long run is small and of
opposite value, requiring that the
1.2
a condition that such
a latch cannot fulfill in 28-nm technology.
We, therefore, resort to current-mode
logic (CML) and construct
the latch illustrated in Figure 5 [9].
Here, the circuit senses the input
when M5
is on and regenerates when
M6 is on. To save voltage headroom,
the bias currents of M5
and M6
defined by a mirror arrangement
rather than by a tail current source.
The latch design begins with a
power budget, e.g., 1 mW. We bias
M5
rises to
about 1 mA when CK is high and M6
is off, and vice versa. To carry a peak
tail current of 1 mA, M1
-M4
and M .6
14 n=
RD
and M6 at a drain current ID of
0.5 mA, assuming that ID5
must
be wide enough so as to leave sufficient
headroom for M5
-
We
then select (/ )/WL 530mnm.
The voltage swings at X and Y are
FIGURE 5: The CML latch design.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
9
Din
+
Din
-
CK
XY
M1 M2
c1
M5
M6
are
FIGURE 4: The impulse response observed at the channel and CTLE outputs.
VDD
RD
M3
M4
c2
CK RB
M7
RB
IR
W1-4 = 5 µm
W5-7 = 2.5 µm
L = 30 nm
RD = 500 Ω
RB = 5 kΩ
C1,2 = 75 fF
VDD
0.5 mA
0.2
0.4
0.6
0.8
1
050
100
Time (ps)
150
200
Channel Output
CTLE Output
Voltage (mV)
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