IEEE Solid-States Circuits Magazine - Winter 2023 - 27

quantities in the surrounding physical
environment. All analog processing
is potentially attacked during
malicious attempts at the theft and
alteration of
analog information,
as depicted in Figure 2(b). Analog
information is protected with secure
analog front ends and followed by
digital cryptography. These analog
techniques enhance analog security
in the front end. The combination of
digital and analog techniques, as in
radio and audio systems, will functionally
provide resiliency against
implementation attacks at the circuit
level, realize detectability and even
predictability in the operation field,
and reach truly system-wide security
through cross-layer developments. A
general overview of such technology
layers is given in Figure 3, showing
that multidisciplinary practices are
key to achieve higher levels of security
against implementation attacks
with a variety of physical properties.
The remainder of this brief article
is constructed as follows. The
" Analog Techniques Assisting Digital
Cryptography " section describes
the analog techniques that combat
implementation attacks. The " Analog
Techniques Enhancing Analog
Security " section discusses the analog
techniques to protect analog
information. The " Future Works " section
provides a brief summary and
future works.
Analog Techniques Assisting
Digital Cryptography
Once a cryptographic algorithm is
embodied as a digital crypto engine
and integrated in a digital part of an
SoC, the chip is under the threat of
implementation attacks.
Passive Attacks and
Countermeasures
It is essential for passive attacks
that digital circuits consume power
in logical switching and that the
demand current, in total, of every
switching event emits EM waves
as well as creates voltage variation
on the PDN. We prepared an IC that
embeds crypto cores and on-chip
power noise monitors and exhibited
power voltage waveforms during
crypto operation. The high and low
sides of the power rails, VDD and VSS,
respectively, are on-chip measured
for voltage waveforms, as shown in
Figure 4. The waveforms for VDD and
VSS are almost symmetric, while the
direction and amplitude are different,
as we clearly see in large negative
drops and small positive spikes,
respectively. This naturally comes
from the power current flowing
from the high side to the low side of
an on-chip PDN, namely, that from
an external power source to the system
ground. The power current and
induced voltages are simulated with
a full-stack model including an IC,
packaging, and a PCB [5].
Digital Data
Plain
Crypto Engine
Cypher
Analog Property
(e.g., EM and Timing)
Encryption
Decryption
Side Channel
Leakage
Suppressor
Side Channel
Attack Sensor
Cypher
Plain
Side
Channel Attack
(Passive and Active)
(a)
Analog
Information
Secure Analog
Front End
Secure
Sensor
Secure
Actuator
Secure
DAC
Secure
DAC
Digital
Back End
DSP
Core
Crypto
Engine
Digital
Data
Cypher
Analog Attack (Deception and Theft)
(b)
FIGURE 2: The analog techniques to (a) protect digital security and (b) prevent analog attacks.
Manufacturing Level
e.g., Supply Chain Integrity and Management of Crypto Keys
Logic Design Level
e.g., Secure Zone and Tamper-Resilient Crypto Cores
Circuit Design Level
e.g., Attack Detector and PUF
Assembly and Device Level
e.g., Secure Packaging and Camouflage
FIGURE 3: The cross-technology layers for the development of hardware security.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2023
27

IEEE Solid-States Circuits Magazine - Winter 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2023