IEEE Solid-States Circuits Magazine - Winter 2023 - 31

analog side channels by introducing
random dithering to suppress the
analog leakage from analog reference
voltage channels [17] and by
using power current equalization to
eliminate analog leakage through
analog power rails [18], both in a SAR
ADC architecture. The susceptibility
of ADCs to intentional EM irradiation
is measured in VCO-based architectures
[19], which potentially leads to
active attacks. The details of those
ADC circuits are available in the
respective papers.
Future Works
Hardware security uses analog techniques
that are complementary to digital
security. This brief article outlined
the main points, and there are relevant
tutorials in [20] and [21]. As inspired by
" slightly analog techniques for security "
suggested by Prof. Verbauwhede
during the NII Shonan Meeting, analog
knowledge has been referenced and
deployed in the design and implementation
of digital systems for security
and authenticity. Key challenges in
the future include the development of
system-level countermeasures to both
passive and active attacks on analog-
digital applications and principles to
assess their security. Further explorations
will surely continue through
tight connections and wide collaborations
among cross-layer communities
of hardware security.
Acknowledgment
We thank to Prof. Kazuo Sakiyama,
University of Electro-Communications;
Prof. Naofumi Homma, Tohoku
University; and Prof. Yuichi Hayashi,
Nara Advanced Institute of Technology,
for fruitful discussions and collaborative
work on hardware security,
in deep association with Prof. Ingrid
Verbauwhede. This work was, in part,
based on the results obtained from a
project, JPNP16007, commissioned by
the New Energy and Industrial Technology
Development Organization.
This work was also, in part, supported
by Japan Society for the Promotion of
Science Grants-in-Aid for Scientific
Research, under grant JP22H04999.
The power current is an analog quantity
inherent to the digital implementation of
a crypto core, and it is very difficult to erase
its time variation.
References
[1] K. Sakiyama, P. Schaumont, and I. Verbauwhede,
" Design methods for secure
hardware, " National Institute of Informatics
SHONAN Meeting, Tokyo, Japan,
Sep. 2014. Accessed: Oct. 1, 2022. [Online].
Available: https://shonan.nii.ac.jp/
seminars/028/
[2] I. Verbauwhede, " Security adds an extra
dimension to IC design: Future IC design
must focus on security in addition to low
power and energy, " IEEE Solid-State Circuits
Mag., vol. 9, no. 4, pp. 41-45, Fall
2017, doi: 10.1109/MSSC.2017.2745799.
[3] M. Alioto, " Trends in hardware security:
From basics to ASICs, " IEEE Solid-State
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Summer 2019, doi: 10.1109/MSSC.2019.
2923503.
[4] R. T. Yazicigil et al., " Beyond crypto: Physical-layer
security for Internet of Things
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10.1109/MSSC.2020.3021842.
[5] A. Tsukioka et al., " A fast side-channel
leakage simulation technique based on IC
chip power modeling, " IEEE Lett. Electromagn.
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[6]
C. Tokunaga and D. Blaauw, " Securing encryption
systems with a switched capacitor
current equalizer, " IEEE J. Solid-State
Circuits, vol. 45, no. 1, pp. 23-31, Jan.
2010, doi: 10.1109/JSSC.2009.2034081.
[7] N. Miura, D. Fujimoto, R. Korenaga, K.
Matsuda, and M. Nagata, " An intermittentdriven
supply-current equalizer for 11x
and 4x power-overhead savings in CPA-resistant
128bit AES cryptographic processor, "
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Circuits Conf. (A-SSCC), pp. 225-228, doi:
10.1109/ASSCC.2014.7008901.
[8] A. Singh et al., " Enhanced power and electromagnetic
SCA resistance of encryption
engines via a security-aware integrated
all-digital LDO, " IEEE J. Solid-State
Circuits, vol. 55, no. 2, pp. 478-493, Feb.
2020, doi: 10.1109/JSSC.2019.2945944.
[9] A. Ghosh, D. Das, J. Danial, V. De, S.
Ghosh, and S. Sen, " Syn-STELLAR: An
EM/power SCA-resilient AES-256 with
synthesis-friendly signature attenuation, "
IEEE J. Solid-State Circuits, vol. 57, no. 1,
pp. 167-181, Jan. 2022, doi: 10.1109/JSSC.
2021.3113335.
[10] N. Homma et al., " Design methodology
and validity verification for a reactive
countermeasure against EM attacks, " J.
Cryptol., vol. 30, no. 2, pp. 373-391, 2017,
doi: 10.1007/s00145-015-9223-3.
[11] S. Tada et al., " Design and concept proof
of an inductive impulse self-destructor in
sense-and-react countermeasure against
physical attacks, " Japanese J. Appl. Phys.,
vol. 60, no. SB, p. SBBL01_1-8, Feb. 2021,
doi: 10.35848/1347-4065/abdf1f.
[12] K. Matsuda et al., " A 286 F2/cell distributed
bulk-current sensor and secure
flush code eraser against laser fault injection
attack on cryptographic processor, "
IEEE J. Solid-State Circuits, vol. 53, no. 11,
pp. 3174-3182, Nov. 2018, doi: 10.1109/
JSSC.2018.2869142.
[13] N. Miura et al., " PLL to the rescue: A novel EM
fault countermeasure, " in Proc. 2016 53nd
ACM/EDAC/IEEE Des. Autom. Conf. (DAC),
pp. 1-6, doi: 10.1145/2897937.2898065.
[14] T. Miki et al., " Si-backside protection circuits
against physical security attacks on
flip-chip devices, " IEEE J. Solid-State Circuits,
vol. 55, no. 10, pp. 2747-2755, Oct.
2020, doi: 10.1109/JSSC.2020.3005779.
[15] K. Monta et al., " 3-D CMOS chip stacking
for security ICs featuring backside
buried metal power delivery networks
with distributed capacitance, " IEEE Trans.
Electron. Devices, vol. 68, no. 4, pp. 2077-
2082, Apr. 2021, doi: 10.1109/TED.2021.
3058226.
[16] S. Nashimoto et al., " Low-cost distancespoofing
attack on FMCW radar and its
feasibility study on countermeasure, "
J. Cryptographic Eng., vol. 11, no. 3, pp.
289-298, 2021, doi: 10.1007/s13389-02000252-5.
[17]
T. Miki, N. Miura, H. Sonoda, K. Mizuta, and
M. Nagata, " A random interrupt dithering
SAR technique for secure ADC against reference-charge
side-channel attack, " IEEE
Trans. Circuits Syst., II, Exp. Briefs, vol. 67,
no. 1, pp. 14-18, Jan. 2020, doi: 10.1109/
TCSII.2019.2901534.
[18] T. Jeong, A. P. Chandrakasan, and H.-S.
Lee, " S2ADC: A 12-bit, 1.25-MS/s secure
SAR ADC with power side-channel attack
resistance, " IEEE J. Solid-State Circuits,
vol. 56, no. 3, pp. 844-854, Mar. 2021, doi:
10.1109/JSSC.2020.3027806.
[19] H. Sonoda, T. Miki, and M. Nagata, " Measurement
of electromagnetic field immunity
of voltage-controlled oscillatorbased
analog-to-digital converters in 28
nm CMOS technology, " Japanese J. Appl.
Phys., vol. 61, no. SC, pp. 1-7, Feb. 2022,
doi: 10.35848/1347-4065/ac48d5.
[20] M. Nagata, T. Miki, and N. Miura, " Physical
attack protection techniques for IC chip
level hardware security, " IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 30, no.
1, pp. 5-14, Jan. 2022, doi: 10.1109/TVLSI.2021.3073946.
[21]
M. Nagata. Hardware Security and Safety of
IC Chips. (Apr. 2021). Accessed: Oct. 1, 2022.
[Online Video]. Available: https://www.
youtube.com/watch?v=M3c_x9e4y8I
About the Authors
Makoto Nagata (nagata@cs.kobe-u.
ac.jp) is with Kobe University, Kobe
657-8501, Japan.
Noriyuki Miura (nmiura@ist.osaka
-u.ac.jp) is with Osaka University, Suita
565-0871, Japan.
Takuji Miki (miki@cs26.scitec.
kobe-u.ac.jp) is with Kobe University,
Kobe 657-8501, Japan.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2023
31
https://shonan.nii.ac.jp/seminars/028/ https://shonan.nii.ac.jp/seminars/028/ https://www.youtube.com/watch?v=M3c_x9e4y8I https://www.youtube.com/watch?v=M3c_x9e4y8I
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